Chris Brandt f08578e6da ARM: 8661/1: dts: r7s72100: add l2 cache ... Note that early-bresp-disable and full-line-zero-disable are required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>		2017-03-17 10:01:28 +00:00
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bootp
compressed	Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm	2017-02-28 11:50:53 -08:00
dts	ARM: 8661/1: dts: r7s72100: add l2 cache	2017-03-17 10:01:28 +00:00
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