forked from Minki/linux
c1ec516030
A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk has 2 bits selecting between 3 possible parents using values of 0, 1, 2, which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in its flag. However we do not support parent 1 (an external clock), so use a table to select parent 0 or 2, which are the 2 parents we support. Note this has not been causing any issues sofar, because we start with a parent setting of parent 0, and only ever re-parent to parent 2 (for which we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set we write a value of 2 for index 1. Tested on both a cubietruck (which uses rgmii mode) as well as a cs908 (an a31s board which uses mii mode). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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| .. | ||
| clk-a10-hosc.c | ||
| clk-a20-gmac.c | ||
| clk-factors.c | ||
| clk-factors.h | ||
| clk-mod0.c | ||
| clk-sun6i-apb0-gates.c | ||
| clk-sun6i-apb0.c | ||
| clk-sun6i-ar100.c | ||
| clk-sun8i-apb0.c | ||
| clk-sun8i-mbus.c | ||
| clk-sun9i-core.c | ||
| clk-sunxi.c | ||
| Makefile | ||