forked from Minki/linux
9859cd3b15
The DU0 clock is an MSTP clock, child of the CPG ZX clock. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright 2013 Ideas On Board SPRL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
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#define __DT_BINDINGS_CLOCK_R8A7794_H__
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/* CPG */
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#define R8A7794_CLK_MAIN 0
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#define R8A7794_CLK_PLL0 1
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#define R8A7794_CLK_PLL1 2
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#define R8A7794_CLK_PLL3 3
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#define R8A7794_CLK_LB 4
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#define R8A7794_CLK_QSPI 5
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#define R8A7794_CLK_SDH 6
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#define R8A7794_CLK_SD0 7
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#define R8A7794_CLK_Z 8
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/* MSTP0 */
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#define R8A7794_CLK_MSIOF0 0
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/* MSTP1 */
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#define R8A7794_CLK_VCP0 1
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#define R8A7794_CLK_VPC0 3
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#define R8A7794_CLK_TMU1 11
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#define R8A7794_CLK_3DG 12
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#define R8A7794_CLK_2DDMAC 15
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#define R8A7794_CLK_FDP1_0 19
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#define R8A7794_CLK_TMU3 21
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#define R8A7794_CLK_TMU2 22
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#define R8A7794_CLK_CMT0 24
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#define R8A7794_CLK_TMU0 25
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#define R8A7794_CLK_VSP1_DU0 28
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#define R8A7794_CLK_VSP1_S 31
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/* MSTP2 */
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#define R8A7794_CLK_SCIFA2 2
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#define R8A7794_CLK_SCIFA1 3
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#define R8A7794_CLK_SCIFA0 4
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#define R8A7794_CLK_MSIOF2 5
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#define R8A7794_CLK_SCIFB0 6
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#define R8A7794_CLK_SCIFB1 7
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#define R8A7794_CLK_MSIOF1 8
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#define R8A7794_CLK_SCIFB2 16
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#define R8A7794_CLK_SYS_DMAC1 18
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#define R8A7794_CLK_SYS_DMAC0 19
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/* MSTP3 */
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#define R8A7794_CLK_SDHI2 11
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#define R8A7794_CLK_SDHI1 12
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#define R8A7794_CLK_SDHI0 14
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#define R8A7794_CLK_MMCIF0 15
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#define R8A7794_CLK_CMT1 29
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#define R8A7794_CLK_USBDMAC0 30
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#define R8A7794_CLK_USBDMAC1 31
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/* MSTP4 */
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#define R8A7794_CLK_IRQC 7
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/* MSTP5 */
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#define R8A7794_CLK_THERMAL 22
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#define R8A7794_CLK_PWM 23
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/* MSTP7 */
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#define R8A7794_CLK_EHCI 3
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#define R8A7794_CLK_HSUSB 4
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#define R8A7794_CLK_HSCIF2 13
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#define R8A7794_CLK_SCIF5 14
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#define R8A7794_CLK_SCIF4 15
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#define R8A7794_CLK_HSCIF1 16
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#define R8A7794_CLK_HSCIF0 17
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#define R8A7794_CLK_SCIF3 18
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#define R8A7794_CLK_SCIF2 19
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#define R8A7794_CLK_SCIF1 20
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#define R8A7794_CLK_SCIF0 21
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#define R8A7794_CLK_DU0 24
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/* MSTP8 */
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#define R8A7794_CLK_VIN1 10
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#define R8A7794_CLK_VIN0 11
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#define R8A7794_CLK_ETHER 13
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/* MSTP9 */
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#define R8A7794_CLK_GPIO6 5
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#define R8A7794_CLK_GPIO5 7
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#define R8A7794_CLK_GPIO4 8
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#define R8A7794_CLK_GPIO3 9
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#define R8A7794_CLK_GPIO2 10
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#define R8A7794_CLK_GPIO1 11
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#define R8A7794_CLK_GPIO0 12
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#define R8A7794_CLK_QSPI_MOD 17
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#define R8A7794_CLK_I2C5 25
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#define R8A7794_CLK_I2C4 27
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#define R8A7794_CLK_I2C3 28
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#define R8A7794_CLK_I2C2 29
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#define R8A7794_CLK_I2C1 30
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#define R8A7794_CLK_I2C0 31
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/* MSTP11 */
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#define R8A7794_CLK_SCIFA3 6
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#define R8A7794_CLK_SCIFA4 7
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#define R8A7794_CLK_SCIFA5 8
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#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
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