forked from Minki/linux
af06cf6c8c
Add check to make sure that the core is enabled and has outstanding interrupts. The activity bit is masked due to the fact that it will stay active even after the controller has been disabled until the contoller internal state machines have settled. Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
565 lines
14 KiB
C
565 lines
14 KiB
C
/*
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* Synopsys DesignWare I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include "i2c-designware-core.h"
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static char *abort_sources[] = {
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[ABRT_7B_ADDR_NOACK] =
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"slave address not acknowledged (7bit mode)",
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[ABRT_10ADDR1_NOACK] =
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"first address byte not acknowledged (10bit mode)",
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[ABRT_10ADDR2_NOACK] =
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"second address byte not acknowledged (10bit mode)",
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[ABRT_TXDATA_NOACK] =
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"data not acknowledged",
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[ABRT_GCALL_NOACK] =
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"no acknowledgement for a general call",
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[ABRT_GCALL_READ] =
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"read after general call",
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[ABRT_SBYTE_ACKDET] =
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"start byte acknowledged",
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[ABRT_SBYTE_NORSTRT] =
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"trying to send start byte when restart is disabled",
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[ABRT_10B_RD_NORSTRT] =
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"trying to read when restart is disabled (10bit mode)",
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[ABRT_MASTER_DIS] =
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"trying to use disabled adapter",
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[ARB_LOST] =
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"lost arbitration",
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};
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u32 dw_readl(struct dw_i2c_dev *dev, int offset)
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{
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u32 value = readl(dev->base + offset);
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if (dev->swab)
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return swab32(value);
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else
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return value;
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}
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void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
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{
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if (dev->swab)
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b = swab32(b);
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writel(b, dev->base + offset);
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}
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static u32
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i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
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{
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/*
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* DesignWare I2C core doesn't seem to have solid strategy to meet
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* the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
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* will result in violation of the tHD;STA spec.
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*/
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if (cond)
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
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*
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* This is based on the DW manuals, and represents an ideal
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* configuration. The resulting I2C bus speed will be
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* faster than any of the others.
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*
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* If your hardware is free from tHD;STA issue, try this one.
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*/
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return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
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else
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
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*
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* This is just experimental rule; the tHD;STA period turned
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* out to be proportinal to (_HCNT + 3). With this setting,
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* we could meet both tHIGH and tHD;STA timing specs.
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*
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* If unsure, you'd better to take this alternative.
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*
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* The reason why we need to take into account "tf" here,
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* is the same as described in i2c_dw_scl_lcnt().
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*/
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return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
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}
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static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
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{
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
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*
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* DW I2C core starts counting the SCL CNTs for the LOW period
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* of the SCL clock (tLOW) as soon as it pulls the SCL line.
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* In order to meet the tLOW timing spec, we need to take into
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* account the fall time of SCL signal (tf). Default tf value
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* should be 0.3 us, for safety.
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*/
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return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
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}
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/**
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* i2c_dw_init() - initialize the designware i2c master hardware
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* @dev: device private data
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*
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* This functions configures and enables the I2C master.
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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int i2c_dw_init(struct dw_i2c_dev *dev)
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{
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u32 input_clock_khz;
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u32 hcnt, lcnt;
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u32 reg;
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input_clock_khz = dev->get_clk_rate_khz(dev);
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/* Configure register endianess access */
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reg = dw_readl(dev, DW_IC_COMP_TYPE);
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if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
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dev->swab = 1;
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reg = DW_IC_COMP_TYPE_VALUE;
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}
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if (reg != DW_IC_COMP_TYPE_VALUE) {
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dev_err(dev->dev, "Unknown Synopsys component type: "
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"0x%08x\n", reg);
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return -ENODEV;
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}
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/* Disable the adapter */
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dw_writel(dev, 0, DW_IC_ENABLE);
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/* set standard and fast speed deviders for high/low periods */
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/* Standard-mode */
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hcnt = i2c_dw_scl_hcnt(input_clock_khz,
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40, /* tHD;STA = tHIGH = 4.0 us */
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3, /* tf = 0.3 us */
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(input_clock_khz,
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47, /* tLOW = 4.7 us */
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3, /* tf = 0.3 us */
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0); /* No offset */
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dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
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dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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/* Fast-mode */
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hcnt = i2c_dw_scl_hcnt(input_clock_khz,
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6, /* tHD;STA = tHIGH = 0.6 us */
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3, /* tf = 0.3 us */
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(input_clock_khz,
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13, /* tLOW = 1.3 us */
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3, /* tf = 0.3 us */
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0); /* No offset */
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dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
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dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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/* Configure Tx/Rx FIFO threshold levels */
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dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
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dw_writel(dev, 0, DW_IC_RX_TL);
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/* configure the i2c master */
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dw_writel(dev, dev->master_cfg , DW_IC_CON);
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return 0;
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}
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/*
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* Waiting for bus not busy
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*/
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static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
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{
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int timeout = TIMEOUT;
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while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
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if (timeout <= 0) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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return -ETIMEDOUT;
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}
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timeout--;
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mdelay(1);
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}
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return 0;
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}
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static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 ic_con;
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/* Disable the adapter */
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dw_writel(dev, 0, DW_IC_ENABLE);
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/* set the slave (target) address */
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dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
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/* if the slave address is ten bit address, enable 10BITADDR */
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ic_con = dw_readl(dev, DW_IC_CON);
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
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ic_con |= DW_IC_CON_10BITADDR_MASTER;
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else
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ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
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dw_writel(dev, ic_con, DW_IC_CON);
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/* Enable the adapter */
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dw_writel(dev, 1, DW_IC_ENABLE);
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/* Enable interrupts */
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dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
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}
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/*
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* Initiate (and continue) low level master read/write transaction.
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* This function is only called from i2c_dw_isr, and pumping i2c_msg
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* messages into the tx buffer. Even if the size of i2c_msg data is
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* longer than the size of the tx buffer, it handles everything.
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*/
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void
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i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 intr_mask;
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int tx_limit, rx_limit;
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u32 addr = msgs[dev->msg_write_idx].addr;
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u32 buf_len = dev->tx_buf_len;
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u8 *buf = dev->tx_buf;
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intr_mask = DW_IC_INTR_DEFAULT_MASK;
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for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
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/*
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* if target address has changed, we need to
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* reprogram the target address in the i2c
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* adapter when we are done with this transfer
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*/
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if (msgs[dev->msg_write_idx].addr != addr) {
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dev_err(dev->dev,
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"%s: invalid target address\n", __func__);
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dev->msg_err = -EINVAL;
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break;
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}
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if (msgs[dev->msg_write_idx].len == 0) {
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dev_err(dev->dev,
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"%s: invalid message length\n", __func__);
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dev->msg_err = -EINVAL;
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break;
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}
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if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
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/* new i2c_msg */
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buf = msgs[dev->msg_write_idx].buf;
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buf_len = msgs[dev->msg_write_idx].len;
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}
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tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
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rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
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while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
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if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
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dw_writel(dev, 0x100, DW_IC_DATA_CMD);
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rx_limit--;
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} else
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dw_writel(dev, *buf++, DW_IC_DATA_CMD);
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tx_limit--; buf_len--;
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}
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dev->tx_buf = buf;
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dev->tx_buf_len = buf_len;
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if (buf_len > 0) {
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/* more bytes to be written */
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dev->status |= STATUS_WRITE_IN_PROGRESS;
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break;
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} else
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dev->status &= ~STATUS_WRITE_IN_PROGRESS;
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}
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/*
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* If i2c_msg index search is completed, we don't need TX_EMPTY
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* interrupt any more.
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*/
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if (dev->msg_write_idx == dev->msgs_num)
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intr_mask &= ~DW_IC_INTR_TX_EMPTY;
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if (dev->msg_err)
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intr_mask = 0;
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dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
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}
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static void
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i2c_dw_read(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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int rx_valid;
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for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
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u32 len;
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u8 *buf;
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if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
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continue;
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if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
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len = msgs[dev->msg_read_idx].len;
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buf = msgs[dev->msg_read_idx].buf;
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} else {
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len = dev->rx_buf_len;
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buf = dev->rx_buf;
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}
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rx_valid = dw_readl(dev, DW_IC_RXFLR);
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for (; len > 0 && rx_valid > 0; len--, rx_valid--)
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*buf++ = dw_readl(dev, DW_IC_DATA_CMD);
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if (len > 0) {
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dev->status |= STATUS_READ_IN_PROGRESS;
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dev->rx_buf_len = len;
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dev->rx_buf = buf;
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return;
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} else
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dev->status &= ~STATUS_READ_IN_PROGRESS;
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}
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}
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static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
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{
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unsigned long abort_source = dev->abort_source;
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int i;
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if (abort_source & DW_IC_TX_ABRT_NOACK) {
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for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
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dev_dbg(dev->dev,
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"%s: %s\n", __func__, abort_sources[i]);
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return -EREMOTEIO;
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}
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for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
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dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
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if (abort_source & DW_IC_TX_ARB_LOST)
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return -EAGAIN;
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else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
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return -EINVAL; /* wrong msgs[] data */
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else
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return -EIO;
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}
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/*
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* Prepare controller for a transaction and call i2c_dw_xfer_msg
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*/
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int
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i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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int ret;
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dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
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mutex_lock(&dev->lock);
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INIT_COMPLETION(dev->cmd_complete);
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dev->msgs = msgs;
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dev->msgs_num = num;
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dev->cmd_err = 0;
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dev->msg_write_idx = 0;
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dev->msg_read_idx = 0;
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dev->msg_err = 0;
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dev->status = STATUS_IDLE;
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dev->abort_source = 0;
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ret = i2c_dw_wait_bus_not_busy(dev);
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if (ret < 0)
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goto done;
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/* start the transfers */
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i2c_dw_xfer_init(dev);
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/* wait for tx to complete */
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ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
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if (ret == 0) {
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dev_err(dev->dev, "controller timed out\n");
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i2c_dw_init(dev);
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ret = -ETIMEDOUT;
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goto done;
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} else if (ret < 0)
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goto done;
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if (dev->msg_err) {
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ret = dev->msg_err;
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goto done;
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}
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/* no error */
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if (likely(!dev->cmd_err)) {
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/* Disable the adapter */
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dw_writel(dev, 0, DW_IC_ENABLE);
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ret = num;
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goto done;
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}
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/* We have an error */
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if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
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ret = i2c_dw_handle_tx_abort(dev);
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goto done;
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}
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ret = -EIO;
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done:
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mutex_unlock(&dev->lock);
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return ret;
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}
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u32 i2c_dw_func(struct i2c_adapter *adap)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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return dev->functionality;
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}
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static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
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{
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u32 stat;
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/*
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* The IC_INTR_STAT register just indicates "enabled" interrupts.
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* Ths unmasked raw version of interrupt status bits are available
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* in the IC_RAW_INTR_STAT register.
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*
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* That is,
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* stat = dw_readl(IC_INTR_STAT);
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* equals to,
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* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
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*
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* The raw version might be useful for debugging purposes.
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*/
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stat = dw_readl(dev, DW_IC_INTR_STAT);
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/*
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* Do not use the IC_CLR_INTR register to clear interrupts, or
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* you'll miss some interrupts, triggered during the period from
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* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
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*
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* Instead, use the separately-prepared IC_CLR_* registers.
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*/
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if (stat & DW_IC_INTR_RX_UNDER)
|
|
dw_readl(dev, DW_IC_CLR_RX_UNDER);
|
|
if (stat & DW_IC_INTR_RX_OVER)
|
|
dw_readl(dev, DW_IC_CLR_RX_OVER);
|
|
if (stat & DW_IC_INTR_TX_OVER)
|
|
dw_readl(dev, DW_IC_CLR_TX_OVER);
|
|
if (stat & DW_IC_INTR_RD_REQ)
|
|
dw_readl(dev, DW_IC_CLR_RD_REQ);
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
/*
|
|
* The IC_TX_ABRT_SOURCE register is cleared whenever
|
|
* the IC_CLR_TX_ABRT is read. Preserve it beforehand.
|
|
*/
|
|
dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
|
|
dw_readl(dev, DW_IC_CLR_TX_ABRT);
|
|
}
|
|
if (stat & DW_IC_INTR_RX_DONE)
|
|
dw_readl(dev, DW_IC_CLR_RX_DONE);
|
|
if (stat & DW_IC_INTR_ACTIVITY)
|
|
dw_readl(dev, DW_IC_CLR_ACTIVITY);
|
|
if (stat & DW_IC_INTR_STOP_DET)
|
|
dw_readl(dev, DW_IC_CLR_STOP_DET);
|
|
if (stat & DW_IC_INTR_START_DET)
|
|
dw_readl(dev, DW_IC_CLR_START_DET);
|
|
if (stat & DW_IC_INTR_GEN_CALL)
|
|
dw_readl(dev, DW_IC_CLR_GEN_CALL);
|
|
|
|
return stat;
|
|
}
|
|
|
|
/*
|
|
* Interrupt service routine. This gets called whenever an I2C interrupt
|
|
* occurs.
|
|
*/
|
|
irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
|
|
{
|
|
struct dw_i2c_dev *dev = dev_id;
|
|
u32 stat, enabled;
|
|
|
|
enabled = dw_readl(dev, DW_IC_ENABLE);
|
|
stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
|
|
dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
|
|
dev->adapter.name, enabled, stat);
|
|
if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
|
|
return IRQ_NONE;
|
|
|
|
stat = i2c_dw_read_clear_intrbits(dev);
|
|
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
dev->cmd_err |= DW_IC_ERR_TX_ABRT;
|
|
dev->status = STATUS_IDLE;
|
|
|
|
/*
|
|
* Anytime TX_ABRT is set, the contents of the tx/rx
|
|
* buffers are flushed. Make sure to skip them.
|
|
*/
|
|
dw_writel(dev, 0, DW_IC_INTR_MASK);
|
|
goto tx_aborted;
|
|
}
|
|
|
|
if (stat & DW_IC_INTR_RX_FULL)
|
|
i2c_dw_read(dev);
|
|
|
|
if (stat & DW_IC_INTR_TX_EMPTY)
|
|
i2c_dw_xfer_msg(dev);
|
|
|
|
/*
|
|
* No need to modify or disable the interrupt mask here.
|
|
* i2c_dw_xfer_msg() will take care of it according to
|
|
* the current transmit status.
|
|
*/
|
|
|
|
tx_aborted:
|
|
if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
|
|
complete(&dev->cmd_complete);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|