forked from Minki/linux
aecc787c06
Fix an asymmetry in the io{read|write}XXbe functions in that the
big-endian variants make use of the raw io accessors while the
little-endian variants use the regular accessors. Some architectures
implement barriers to order against both spinlocks and DMA accesses
and for these case, the big-endian variant of the API would not be
protected.
Thus, change the mmio_XXXXbe macros to use the appropriate swab() function
wrapping the regular accessor. This is similar to what was done for PIO.
When this code was originally written, barriers in the IO accessors were
not common and the accessors simply wrapped the raw functions in a
conversion to CPU endianness. Since then, barriers have been added in
some architectures and are now missing in the big endian variant of the
API.
This also manages to silence a few sparse warnings that check
for using the correct endian types which the original code did
not annotate correctly.
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kate Stewart <kstewart@linuxfoundation.org>
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Link: http://lkml.kernel.org/r/CAK8P3a25zQDxyaY3iVv+JmSSzs7F6ssGc+HdBkGs54ZfViX+Fg@mail.gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
254 lines
6.5 KiB
C
254 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Implement the default iomap interfaces
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*
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* (C) Copyright 2004 Linus Torvalds
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*/
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/export.h>
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/*
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* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
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* access or a MMIO access, these functions don't care. The info is
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* encoded in the hardware mapping set up by the mapping functions
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* (or the cookie itself, depending on implementation and hw).
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*
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* The generic routines don't assume any hardware mappings, and just
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* encode the PIO/MMIO as part of the cookie. They coldly assume that
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* the MMIO IO mappings are not in the low address range.
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*
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* Architectures for which this is not true can't use this generic
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* implementation and should do their own copy.
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*/
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#ifndef HAVE_ARCH_PIO_SIZE
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/*
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* We encode the physical PIO addresses (0-0xffff) into the
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* pointer by offsetting them with a constant (0x10000) and
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* assuming that all the low addresses are always PIO. That means
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* we can do some sanity checks on the low bits, and don't
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* need to just take things for granted.
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*/
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#define PIO_OFFSET 0x10000UL
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#define PIO_MASK 0x0ffffUL
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#define PIO_RESERVED 0x40000UL
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#endif
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static void bad_io_access(unsigned long port, const char *access)
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{
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static int count = 10;
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if (count) {
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count--;
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WARN(1, KERN_ERR "Bad IO access at port %#lx (%s)\n", port, access);
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}
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}
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/*
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* Ugly macros are a way of life.
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*/
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#define IO_COND(addr, is_pio, is_mmio) do { \
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unsigned long port = (unsigned long __force)addr; \
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if (port >= PIO_RESERVED) { \
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is_mmio; \
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} else if (port > PIO_OFFSET) { \
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port &= PIO_MASK; \
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is_pio; \
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} else \
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bad_io_access(port, #is_pio ); \
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} while (0)
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#ifndef pio_read16be
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#define pio_read16be(port) swab16(inw(port))
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#define pio_read32be(port) swab32(inl(port))
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#endif
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#ifndef mmio_read16be
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#define mmio_read16be(addr) swab16(readw(addr))
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#define mmio_read32be(addr) swab32(readl(addr))
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#endif
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unsigned int ioread8(void __iomem *addr)
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{
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IO_COND(addr, return inb(port), return readb(addr));
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return 0xff;
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}
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unsigned int ioread16(void __iomem *addr)
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{
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IO_COND(addr, return inw(port), return readw(addr));
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return 0xffff;
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}
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unsigned int ioread16be(void __iomem *addr)
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{
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IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
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return 0xffff;
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}
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unsigned int ioread32(void __iomem *addr)
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{
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IO_COND(addr, return inl(port), return readl(addr));
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return 0xffffffff;
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}
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unsigned int ioread32be(void __iomem *addr)
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{
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IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
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return 0xffffffff;
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}
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EXPORT_SYMBOL(ioread8);
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EXPORT_SYMBOL(ioread16);
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EXPORT_SYMBOL(ioread16be);
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EXPORT_SYMBOL(ioread32);
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EXPORT_SYMBOL(ioread32be);
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#ifndef pio_write16be
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#define pio_write16be(val,port) outw(swab16(val),port)
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#define pio_write32be(val,port) outl(swab32(val),port)
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#endif
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#ifndef mmio_write16be
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#define mmio_write16be(val,port) writew(swab16(val),port)
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#define mmio_write32be(val,port) writel(swab32(val),port)
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#endif
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void iowrite8(u8 val, void __iomem *addr)
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{
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IO_COND(addr, outb(val,port), writeb(val, addr));
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}
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void iowrite16(u16 val, void __iomem *addr)
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{
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IO_COND(addr, outw(val,port), writew(val, addr));
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}
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void iowrite16be(u16 val, void __iomem *addr)
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{
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IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
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}
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void iowrite32(u32 val, void __iomem *addr)
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{
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IO_COND(addr, outl(val,port), writel(val, addr));
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}
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void iowrite32be(u32 val, void __iomem *addr)
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{
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IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
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}
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EXPORT_SYMBOL(iowrite8);
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EXPORT_SYMBOL(iowrite16);
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EXPORT_SYMBOL(iowrite16be);
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EXPORT_SYMBOL(iowrite32);
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EXPORT_SYMBOL(iowrite32be);
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/*
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* These are the "repeat MMIO read/write" functions.
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* Note the "__raw" accesses, since we don't want to
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* convert to CPU byte order. We write in "IO byte
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* order" (we also don't have IO barriers).
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*/
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#ifndef mmio_insb
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static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
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{
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while (--count >= 0) {
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u8 data = __raw_readb(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
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{
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while (--count >= 0) {
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u16 data = __raw_readw(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
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{
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while (--count >= 0) {
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u32 data = __raw_readl(addr);
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*dst = data;
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dst++;
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}
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}
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#endif
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#ifndef mmio_outsb
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static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
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{
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while (--count >= 0) {
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__raw_writeb(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
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{
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while (--count >= 0) {
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__raw_writew(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
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{
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while (--count >= 0) {
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__raw_writel(*src, addr);
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src++;
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}
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}
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#endif
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void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
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}
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void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
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}
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void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
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}
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EXPORT_SYMBOL(ioread8_rep);
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EXPORT_SYMBOL(ioread16_rep);
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EXPORT_SYMBOL(ioread32_rep);
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void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
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}
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void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
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}
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void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
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}
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EXPORT_SYMBOL(iowrite8_rep);
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EXPORT_SYMBOL(iowrite16_rep);
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EXPORT_SYMBOL(iowrite32_rep);
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#ifdef CONFIG_HAS_IOPORT_MAP
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/* Create a virtual mapping cookie for an IO port range */
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void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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if (port > PIO_MASK)
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return NULL;
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return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
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}
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void ioport_unmap(void __iomem *addr)
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{
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/* Nothing to do */
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}
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EXPORT_SYMBOL(ioport_map);
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EXPORT_SYMBOL(ioport_unmap);
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#endif /* CONFIG_HAS_IOPORT_MAP */
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#ifdef CONFIG_PCI
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/* Hide the details if this is a MMIO or PIO address space and just do what
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* you expect in the correct way. */
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void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
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{
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IO_COND(addr, /* nothing */, iounmap(addr));
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}
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EXPORT_SYMBOL(pci_iounmap);
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#endif /* CONFIG_PCI */
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