In master mode, SCLK and LRCLK signals are generated by the CODEC when
any of the ADC/DAC are enabled. SCLK is derived from MCLK via a
programmable division set by BLK_DIV, LRCLK is derived from MCLK via
another programmable division set by ADCFsRatio/DACFsRatio.
In slave mode, SCLK and LRCLK signals are received as inputs and
supplied externally. LRCLK and SCLK must be synchronously derived from
MCLK with specific rates. The device can auto detect MCLK/LRCLK ratio
according to a predefined table. LRCLK/SCLK ratio is usually 64 (SCLK =
64 * LRCLK)
This commits adds support to let to device auto detect and decide which
ratio to use. The mclkdiv2 and BCLK_DIV ratio and put to zero.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
ae884ae78a