e2b397f18c
On recent Broadcom chipsets PMU is present as separated core and it can't be accessed using ChipCommon anymore as it fails with e.g.: [ 18.198412] Unhandled fault: imprecise external abort (0x1406) at 0xb6da200f Add a new helper function that will return a proper core that should be used for accessing PMU registers. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
/*
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* Copyright (c) 2014 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef BRCMF_CHIP_H
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#define BRCMF_CHIP_H
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#include <linux/types.h>
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#define CORE_CC_REG(base, field) \
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(base + offsetof(struct chipcregs, field))
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/**
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* struct brcmf_chip - chip level information.
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*
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* @chip: chip identifier.
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* @chiprev: chip revision.
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* @cc_caps: chipcommon core capabilities.
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* @cc_caps_ext: chipcommon core extended capabilities.
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* @pmucaps: PMU capabilities.
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* @pmurev: PMU revision.
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* @rambase: RAM base address (only applicable for ARM CR4 chips).
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* @ramsize: amount of RAM on chip including retention.
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* @srsize: amount of retention RAM on chip.
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* @name: string representation of the chip identifier.
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*/
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struct brcmf_chip {
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u32 chip;
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u32 chiprev;
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u32 cc_caps;
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u32 cc_caps_ext;
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u32 pmucaps;
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u32 pmurev;
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u32 rambase;
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u32 ramsize;
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u32 srsize;
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char name[8];
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};
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/**
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* struct brcmf_core - core related information.
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*
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* @id: core identifier.
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* @rev: core revision.
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* @base: base address of core register space.
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*/
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struct brcmf_core {
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u16 id;
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u16 rev;
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u32 base;
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};
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/**
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* struct brcmf_buscore_ops - buscore specific callbacks.
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*
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* @read32: read 32-bit value over bus.
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* @write32: write 32-bit value over bus.
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* @prepare: prepare bus for core configuration.
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* @setup: bus-specific core setup.
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* @active: chip becomes active.
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* The callback should use the provided @rstvec when non-zero.
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*/
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struct brcmf_buscore_ops {
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u32 (*read32)(void *ctx, u32 addr);
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void (*write32)(void *ctx, u32 addr, u32 value);
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int (*prepare)(void *ctx);
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int (*reset)(void *ctx, struct brcmf_chip *chip);
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int (*setup)(void *ctx, struct brcmf_chip *chip);
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void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec);
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};
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struct brcmf_chip *brcmf_chip_attach(void *ctx,
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const struct brcmf_buscore_ops *ops);
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void brcmf_chip_detach(struct brcmf_chip *chip);
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struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid);
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struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *chip);
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struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub);
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bool brcmf_chip_iscoreup(struct brcmf_core *core);
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void brcmf_chip_coredisable(struct brcmf_core *core, u32 prereset, u32 reset);
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void brcmf_chip_resetcore(struct brcmf_core *core, u32 prereset, u32 reset,
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u32 postreset);
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void brcmf_chip_set_passive(struct brcmf_chip *ci);
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bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec);
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bool brcmf_chip_sr_capable(struct brcmf_chip *pub);
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#endif /* BRCMF_AXIDMP_H */
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