Joseph Gravenor ac81c2a75b drm/amd/display: add guard for SMU ver, for 48mhz clk ... [why] dp_48m_refclk_driver_pwdn is persistent through S3 and S5. This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix so we will hang on reboot [how] add a guard for smu versions before SMU FW 55.21.0 Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-10-10 19:33:23 -05:00
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dce100	drm/amd/display: make firmware info only load once during dc_bios create	2019-08-15 10:53:36 -05:00
dce110	drm/amdgpu/display: fix 64 bit divide	2019-10-03 09:11:00 -05:00
dce112	drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct	2019-07-18 14:18:09 -05:00
dce120	drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct	2019-07-18 14:18:09 -05:00
dcn10	drm/amd/display: remove hw access from dc_destroy	2019-09-13 18:02:52 -05:00
dcn20	drm/amd/display: add explicit comparator as default optimization check	2019-10-10 19:31:35 -05:00
dcn21	drm/amd/display: add guard for SMU ver, for 48mhz clk	2019-10-10 19:33:23 -05:00
clk_mgr.c	drm/amd/display: exit PSR during detection	2019-10-10 19:33:07 -05:00
Makefile	drm/amd/display: Add Renoir clock manager	2019-08-29 15:52:33 -05:00