forked from Minki/linux
ac620ba3d0
Function zx_find_crtc() does the exactly same thing as what crtc helper drm_crtc_from_index() provides. Use the helper to save some code. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1483015290-16660-3-git-send-email-shawnguo@kernel.org
651 lines
17 KiB
C
651 lines
17 KiB
C
/*
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* Copyright 2016 Linaro Ltd.
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* Copyright 2016 ZTE Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_address.h>
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#include <video/videomode.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_of.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drmP.h>
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#include "zx_drm_drv.h"
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#include "zx_plane.h"
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#include "zx_vou.h"
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#include "zx_vou_regs.h"
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#define GL_NUM 2
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#define VL_NUM 3
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enum vou_chn_type {
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VOU_CHN_MAIN,
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VOU_CHN_AUX,
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};
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struct zx_crtc_regs {
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u32 fir_active;
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u32 fir_htiming;
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u32 fir_vtiming;
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u32 timing_shift;
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u32 timing_pi_shift;
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};
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static const struct zx_crtc_regs main_crtc_regs = {
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.fir_active = FIR_MAIN_ACTIVE,
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.fir_htiming = FIR_MAIN_H_TIMING,
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.fir_vtiming = FIR_MAIN_V_TIMING,
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.timing_shift = TIMING_MAIN_SHIFT,
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.timing_pi_shift = TIMING_MAIN_PI_SHIFT,
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};
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static const struct zx_crtc_regs aux_crtc_regs = {
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.fir_active = FIR_AUX_ACTIVE,
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.fir_htiming = FIR_AUX_H_TIMING,
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.fir_vtiming = FIR_AUX_V_TIMING,
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.timing_shift = TIMING_AUX_SHIFT,
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.timing_pi_shift = TIMING_AUX_PI_SHIFT,
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};
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struct zx_crtc_bits {
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u32 polarity_mask;
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u32 polarity_shift;
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u32 int_frame_mask;
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u32 tc_enable;
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u32 gl_enable;
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};
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static const struct zx_crtc_bits main_crtc_bits = {
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.polarity_mask = MAIN_POL_MASK,
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.polarity_shift = MAIN_POL_SHIFT,
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.int_frame_mask = TIMING_INT_MAIN_FRAME,
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.tc_enable = MAIN_TC_EN,
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.gl_enable = OSD_CTRL0_GL0_EN,
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};
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static const struct zx_crtc_bits aux_crtc_bits = {
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.polarity_mask = AUX_POL_MASK,
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.polarity_shift = AUX_POL_SHIFT,
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.int_frame_mask = TIMING_INT_AUX_FRAME,
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.tc_enable = AUX_TC_EN,
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.gl_enable = OSD_CTRL0_GL1_EN,
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};
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struct zx_crtc {
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struct drm_crtc crtc;
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struct drm_plane *primary;
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struct zx_vou_hw *vou;
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void __iomem *chnreg;
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const struct zx_crtc_regs *regs;
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const struct zx_crtc_bits *bits;
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enum vou_chn_type chn_type;
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struct clk *pixclk;
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};
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#define to_zx_crtc(x) container_of(x, struct zx_crtc, crtc)
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struct zx_vou_hw {
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struct device *dev;
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void __iomem *osd;
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void __iomem *timing;
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void __iomem *vouctl;
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void __iomem *otfppu;
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void __iomem *dtrc;
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struct clk *axi_clk;
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struct clk *ppu_clk;
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struct clk *main_clk;
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struct clk *aux_clk;
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struct zx_crtc *main_crtc;
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struct zx_crtc *aux_crtc;
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};
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static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
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{
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struct zx_crtc *zcrtc = to_zx_crtc(crtc);
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return zcrtc->vou;
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}
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void vou_inf_enable(const struct vou_inf *inf, struct drm_crtc *crtc)
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{
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struct zx_crtc *zcrtc = to_zx_crtc(crtc);
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struct zx_vou_hw *vou = zcrtc->vou;
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bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
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u32 data_sel_shift = inf->id << 1;
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/* Select data format */
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zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
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inf->data_sel << data_sel_shift);
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/* Select channel */
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zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << inf->id,
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zcrtc->chn_type << inf->id);
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/* Select interface clocks */
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zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,
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is_main ? 0 : inf->clocks_sel_bits);
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/* Enable interface clocks */
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zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,
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inf->clocks_en_bits);
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/* Enable the device */
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zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << inf->id, 1 << inf->id);
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}
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void vou_inf_disable(const struct vou_inf *inf, struct drm_crtc *crtc)
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{
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struct zx_vou_hw *vou = crtc_to_vou(crtc);
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/* Disable the device */
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zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << inf->id, 0);
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/* Disable interface clocks */
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zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
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}
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static inline void vou_chn_set_update(struct zx_crtc *zcrtc)
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{
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zx_writel(zcrtc->chnreg + CHN_UPDATE, 1);
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}
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static void zx_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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struct zx_crtc *zcrtc = to_zx_crtc(crtc);
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struct zx_vou_hw *vou = zcrtc->vou;
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const struct zx_crtc_regs *regs = zcrtc->regs;
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const struct zx_crtc_bits *bits = zcrtc->bits;
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struct videomode vm;
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u32 pol = 0;
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u32 val;
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int ret;
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drm_display_mode_to_videomode(mode, &vm);
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/* Set up timing parameters */
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val = V_ACTIVE(vm.vactive - 1);
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val |= H_ACTIVE(vm.hactive - 1);
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zx_writel(vou->timing + regs->fir_active, val);
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val = SYNC_WIDE(vm.hsync_len - 1);
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val |= BACK_PORCH(vm.hback_porch - 1);
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val |= FRONT_PORCH(vm.hfront_porch - 1);
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zx_writel(vou->timing + regs->fir_htiming, val);
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val = SYNC_WIDE(vm.vsync_len - 1);
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val |= BACK_PORCH(vm.vback_porch - 1);
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val |= FRONT_PORCH(vm.vfront_porch - 1);
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zx_writel(vou->timing + regs->fir_vtiming, val);
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/* Set up polarities */
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if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
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pol |= 1 << POL_VSYNC_SHIFT;
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if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW)
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pol |= 1 << POL_HSYNC_SHIFT;
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zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,
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pol << bits->polarity_shift);
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/* Setup SHIFT register by following what ZTE BSP does */
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zx_writel(vou->timing + regs->timing_shift, H_SHIFT_VAL);
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zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL);
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/* Enable TIMING_CTRL */
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zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,
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bits->tc_enable);
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/* Configure channel screen size */
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zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_W_MASK,
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vm.hactive << CHN_SCREEN_W_SHIFT);
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zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_H_MASK,
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vm.vactive << CHN_SCREEN_H_SHIFT);
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/* Update channel */
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vou_chn_set_update(zcrtc);
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/* Enable channel */
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zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, CHN_ENABLE);
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/* Enable Graphic Layer */
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zx_writel_mask(vou->osd + OSD_CTRL0, bits->gl_enable,
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bits->gl_enable);
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drm_crtc_vblank_on(crtc);
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ret = clk_set_rate(zcrtc->pixclk, mode->clock * 1000);
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if (ret) {
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DRM_DEV_ERROR(vou->dev, "failed to set pixclk rate: %d\n", ret);
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return;
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}
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ret = clk_prepare_enable(zcrtc->pixclk);
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if (ret)
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DRM_DEV_ERROR(vou->dev, "failed to enable pixclk: %d\n", ret);
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}
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static void zx_crtc_disable(struct drm_crtc *crtc)
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{
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struct zx_crtc *zcrtc = to_zx_crtc(crtc);
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const struct zx_crtc_bits *bits = zcrtc->bits;
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struct zx_vou_hw *vou = zcrtc->vou;
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clk_disable_unprepare(zcrtc->pixclk);
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drm_crtc_vblank_off(crtc);
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/* Disable Graphic Layer */
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zx_writel_mask(vou->osd + OSD_CTRL0, bits->gl_enable, 0);
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/* Disable channel */
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zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, 0);
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/* Disable TIMING_CTRL */
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zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);
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}
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static void zx_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct drm_pending_vblank_event *event = crtc->state->event;
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if (!event)
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return;
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crtc->state->event = NULL;
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spin_lock_irq(&crtc->dev->event_lock);
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if (drm_crtc_vblank_get(crtc) == 0)
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drm_crtc_arm_vblank_event(crtc, event);
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else
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drm_crtc_send_vblank_event(crtc, event);
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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static const struct drm_crtc_helper_funcs zx_crtc_helper_funcs = {
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.enable = zx_crtc_enable,
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.disable = zx_crtc_disable,
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.atomic_flush = zx_crtc_atomic_flush,
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};
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static const struct drm_crtc_funcs zx_crtc_funcs = {
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.destroy = drm_crtc_cleanup,
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.set_config = drm_atomic_helper_set_config,
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.page_flip = drm_atomic_helper_page_flip,
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.reset = drm_atomic_helper_crtc_reset,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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};
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static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
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enum vou_chn_type chn_type)
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{
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struct device *dev = vou->dev;
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struct zx_layer_data data;
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struct zx_crtc *zcrtc;
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int ret;
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zcrtc = devm_kzalloc(dev, sizeof(*zcrtc), GFP_KERNEL);
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if (!zcrtc)
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return -ENOMEM;
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zcrtc->vou = vou;
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zcrtc->chn_type = chn_type;
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if (chn_type == VOU_CHN_MAIN) {
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data.layer = vou->osd + MAIN_GL_OFFSET;
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data.csc = vou->osd + MAIN_CSC_OFFSET;
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data.hbsc = vou->osd + MAIN_HBSC_OFFSET;
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data.rsz = vou->otfppu + MAIN_RSZ_OFFSET;
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zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
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zcrtc->regs = &main_crtc_regs;
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zcrtc->bits = &main_crtc_bits;
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} else {
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data.layer = vou->osd + AUX_GL_OFFSET;
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data.csc = vou->osd + AUX_CSC_OFFSET;
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data.hbsc = vou->osd + AUX_HBSC_OFFSET;
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data.rsz = vou->otfppu + AUX_RSZ_OFFSET;
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zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
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zcrtc->regs = &aux_crtc_regs;
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zcrtc->bits = &aux_crtc_bits;
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}
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zcrtc->pixclk = devm_clk_get(dev, (chn_type == VOU_CHN_MAIN) ?
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"main_wclk" : "aux_wclk");
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if (IS_ERR(zcrtc->pixclk)) {
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ret = PTR_ERR(zcrtc->pixclk);
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DRM_DEV_ERROR(dev, "failed to get pix clk: %d\n", ret);
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return ret;
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}
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zcrtc->primary = zx_plane_init(drm, dev, &data, DRM_PLANE_TYPE_PRIMARY);
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if (IS_ERR(zcrtc->primary)) {
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ret = PTR_ERR(zcrtc->primary);
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DRM_DEV_ERROR(dev, "failed to init primary plane: %d\n", ret);
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return ret;
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}
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ret = drm_crtc_init_with_planes(drm, &zcrtc->crtc, zcrtc->primary, NULL,
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&zx_crtc_funcs, NULL);
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if (ret) {
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DRM_DEV_ERROR(dev, "failed to init drm crtc: %d\n", ret);
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return ret;
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}
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drm_crtc_helper_add(&zcrtc->crtc, &zx_crtc_helper_funcs);
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if (chn_type == VOU_CHN_MAIN)
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vou->main_crtc = zcrtc;
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else
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vou->aux_crtc = zcrtc;
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return 0;
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}
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int zx_vou_enable_vblank(struct drm_device *drm, unsigned int pipe)
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{
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struct drm_crtc *crtc;
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struct zx_crtc *zcrtc;
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struct zx_vou_hw *vou;
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u32 int_frame_mask;
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crtc = drm_crtc_from_index(drm, pipe);
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if (!crtc)
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return 0;
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vou = crtc_to_vou(crtc);
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zcrtc = to_zx_crtc(crtc);
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int_frame_mask = zcrtc->bits->int_frame_mask;
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zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask,
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int_frame_mask);
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return 0;
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}
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void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe)
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{
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struct drm_crtc *crtc;
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struct zx_crtc *zcrtc;
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struct zx_vou_hw *vou;
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crtc = drm_crtc_from_index(drm, pipe);
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if (!crtc)
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return;
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vou = crtc_to_vou(crtc);
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zcrtc = to_zx_crtc(crtc);
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zx_writel_mask(vou->timing + TIMING_INT_CTRL,
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zcrtc->bits->int_frame_mask, 0);
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}
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static irqreturn_t vou_irq_handler(int irq, void *dev_id)
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{
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struct zx_vou_hw *vou = dev_id;
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u32 state;
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/* Handle TIMING_CTRL frame interrupts */
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state = zx_readl(vou->timing + TIMING_INT_STATE);
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zx_writel(vou->timing + TIMING_INT_STATE, state);
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if (state & TIMING_INT_MAIN_FRAME)
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drm_crtc_handle_vblank(&vou->main_crtc->crtc);
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if (state & TIMING_INT_AUX_FRAME)
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drm_crtc_handle_vblank(&vou->aux_crtc->crtc);
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/* Handle OSD interrupts */
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state = zx_readl(vou->osd + OSD_INT_STA);
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zx_writel(vou->osd + OSD_INT_CLRSTA, state);
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if (state & OSD_INT_MAIN_UPT) {
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vou_chn_set_update(vou->main_crtc);
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zx_plane_set_update(vou->main_crtc->primary);
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}
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if (state & OSD_INT_AUX_UPT) {
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vou_chn_set_update(vou->aux_crtc);
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zx_plane_set_update(vou->aux_crtc->primary);
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}
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if (state & OSD_INT_ERROR)
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DRM_DEV_ERROR(vou->dev, "OSD ERROR: 0x%08x!\n", state);
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return IRQ_HANDLED;
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}
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static void vou_dtrc_init(struct zx_vou_hw *vou)
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{
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/* Clear bit for bypass by ID */
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zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL,
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TILE2RASTESCAN_BYPASS_MODE, 0);
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/* Select ARIDR mode */
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zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK,
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DETILE_ARID_IN_ARIDR);
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/* Bypass decompression for both frames */
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zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS,
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DTRC_DECOMPRESS_BYPASS);
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zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS,
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DTRC_DECOMPRESS_BYPASS);
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/* Set up ARID register */
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zx_writel(vou->dtrc + DTRC_ARID, DTRC_ARID3(0xf) | DTRC_ARID2(0xe) |
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DTRC_ARID1(0xf) | DTRC_ARID0(0xe));
|
|
}
|
|
|
|
static void vou_hw_init(struct zx_vou_hw *vou)
|
|
{
|
|
/* Set GL0 to main channel and GL1 to aux channel */
|
|
zx_writel_mask(vou->osd + OSD_CTRL0, OSD_CTRL0_GL0_SEL, 0);
|
|
zx_writel_mask(vou->osd + OSD_CTRL0, OSD_CTRL0_GL1_SEL,
|
|
OSD_CTRL0_GL1_SEL);
|
|
|
|
/* Release reset for all VOU modules */
|
|
zx_writel(vou->vouctl + VOU_SOFT_RST, ~0);
|
|
|
|
/* Select main clock for GL0 and aux clock for GL1 module */
|
|
zx_writel_mask(vou->vouctl + VOU_CLK_SEL, VOU_CLK_GL0_SEL, 0);
|
|
zx_writel_mask(vou->vouctl + VOU_CLK_SEL, VOU_CLK_GL1_SEL,
|
|
VOU_CLK_GL1_SEL);
|
|
|
|
/* Enable clock auto-gating for all VOU modules */
|
|
zx_writel(vou->vouctl + VOU_CLK_REQEN, ~0);
|
|
|
|
/* Enable all VOU module clocks */
|
|
zx_writel(vou->vouctl + VOU_CLK_EN, ~0);
|
|
|
|
/* Clear both OSD and TIMING_CTRL interrupt state */
|
|
zx_writel(vou->osd + OSD_INT_CLRSTA, ~0);
|
|
zx_writel(vou->timing + TIMING_INT_STATE, ~0);
|
|
|
|
/* Enable OSD and TIMING_CTRL interrrupts */
|
|
zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE);
|
|
zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE);
|
|
|
|
/* Select GPC as input to gl/vl scaler as a sane default setting */
|
|
zx_writel(vou->otfppu + OTFPPU_RSZ_DATA_SOURCE, 0x2a);
|
|
|
|
/*
|
|
* Needs to reset channel and layer logic per frame when frame starts
|
|
* to get VOU work properly.
|
|
*/
|
|
zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);
|
|
|
|
vou_dtrc_init(vou);
|
|
}
|
|
|
|
static int zx_crtc_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct drm_device *drm = data;
|
|
struct zx_vou_hw *vou;
|
|
struct resource *res;
|
|
int irq;
|
|
int ret;
|
|
|
|
vou = devm_kzalloc(dev, sizeof(*vou), GFP_KERNEL);
|
|
if (!vou)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "osd");
|
|
vou->osd = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(vou->osd)) {
|
|
ret = PTR_ERR(vou->osd);
|
|
DRM_DEV_ERROR(dev, "failed to remap osd region: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "timing_ctrl");
|
|
vou->timing = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(vou->timing)) {
|
|
ret = PTR_ERR(vou->timing);
|
|
DRM_DEV_ERROR(dev, "failed to remap timing_ctrl region: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dtrc");
|
|
vou->dtrc = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(vou->dtrc)) {
|
|
ret = PTR_ERR(vou->dtrc);
|
|
DRM_DEV_ERROR(dev, "failed to remap dtrc region: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vou_ctrl");
|
|
vou->vouctl = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(vou->vouctl)) {
|
|
ret = PTR_ERR(vou->vouctl);
|
|
DRM_DEV_ERROR(dev, "failed to remap vou_ctrl region: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otfppu");
|
|
vou->otfppu = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(vou->otfppu)) {
|
|
ret = PTR_ERR(vou->otfppu);
|
|
DRM_DEV_ERROR(dev, "failed to remap otfppu region: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
vou->axi_clk = devm_clk_get(dev, "aclk");
|
|
if (IS_ERR(vou->axi_clk)) {
|
|
ret = PTR_ERR(vou->axi_clk);
|
|
DRM_DEV_ERROR(dev, "failed to get axi_clk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
vou->ppu_clk = devm_clk_get(dev, "ppu_wclk");
|
|
if (IS_ERR(vou->ppu_clk)) {
|
|
ret = PTR_ERR(vou->ppu_clk);
|
|
DRM_DEV_ERROR(dev, "failed to get ppu_clk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(vou->axi_clk);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(dev, "failed to enable axi_clk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
clk_prepare_enable(vou->ppu_clk);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(dev, "failed to enable ppu_clk: %d\n", ret);
|
|
goto disable_axi_clk;
|
|
}
|
|
|
|
vou->dev = dev;
|
|
dev_set_drvdata(dev, vou);
|
|
|
|
vou_hw_init(vou);
|
|
|
|
ret = devm_request_irq(dev, irq, vou_irq_handler, 0, "zx_vou", vou);
|
|
if (ret < 0) {
|
|
DRM_DEV_ERROR(dev, "failed to request vou irq: %d\n", ret);
|
|
goto disable_ppu_clk;
|
|
}
|
|
|
|
ret = zx_crtc_init(drm, vou, VOU_CHN_MAIN);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(dev, "failed to init main channel crtc: %d\n",
|
|
ret);
|
|
goto disable_ppu_clk;
|
|
}
|
|
|
|
ret = zx_crtc_init(drm, vou, VOU_CHN_AUX);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(dev, "failed to init aux channel crtc: %d\n",
|
|
ret);
|
|
goto disable_ppu_clk;
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_ppu_clk:
|
|
clk_disable_unprepare(vou->ppu_clk);
|
|
disable_axi_clk:
|
|
clk_disable_unprepare(vou->axi_clk);
|
|
return ret;
|
|
}
|
|
|
|
static void zx_crtc_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct zx_vou_hw *vou = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(vou->axi_clk);
|
|
clk_disable_unprepare(vou->ppu_clk);
|
|
}
|
|
|
|
static const struct component_ops zx_crtc_component_ops = {
|
|
.bind = zx_crtc_bind,
|
|
.unbind = zx_crtc_unbind,
|
|
};
|
|
|
|
static int zx_crtc_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &zx_crtc_component_ops);
|
|
}
|
|
|
|
static int zx_crtc_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &zx_crtc_component_ops);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id zx_crtc_of_match[] = {
|
|
{ .compatible = "zte,zx296718-dpc", },
|
|
{ /* end */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, zx_crtc_of_match);
|
|
|
|
struct platform_driver zx_crtc_driver = {
|
|
.probe = zx_crtc_probe,
|
|
.remove = zx_crtc_remove,
|
|
.driver = {
|
|
.name = "zx-crtc",
|
|
.of_match_table = zx_crtc_of_match,
|
|
},
|
|
};
|