667ce33e57
We can have various combinations of 64b and 32b address space, ie. 64b CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So best to decouple the device iova's from mmap offset. Signed-off-by: Rob Clark <robdclark@gmail.com>
560 lines
12 KiB
C
560 lines
12 KiB
C
/*
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* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "mdp5_kms.h"
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#include "mdp5_cfg.h"
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struct mdp5_cfg_handler {
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int revision;
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struct mdp5_cfg config;
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};
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/* mdp5_cfg must be exposed (used in mdp5.xml.h) */
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const struct mdp5_cfg_hw *mdp5_cfg = NULL;
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const struct mdp5_cfg_hw msm8x74v1_config = {
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.name = "msm8x74v1",
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.mdp = {
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.count = 1,
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.caps = MDP_CAP_SMP |
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0,
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},
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.smp = {
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.mmb_count = 22,
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.mmb_size = 4096,
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.clients = {
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[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
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[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
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[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
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},
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},
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.ctl = {
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.count = 5,
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.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
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.flush_hw_mask = 0x0003ffff,
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},
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.pipe_vig = {
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.count = 3,
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.base = { 0x01100, 0x01500, 0x01900 },
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.caps = MDP_PIPE_CAP_HFLIP |
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MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE |
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MDP_PIPE_CAP_CSC |
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0,
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},
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.pipe_rgb = {
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.count = 3,
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.base = { 0x01d00, 0x02100, 0x02500 },
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.caps = MDP_PIPE_CAP_HFLIP |
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MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE |
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0,
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},
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.pipe_dma = {
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.count = 2,
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.base = { 0x02900, 0x02d00 },
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.caps = MDP_PIPE_CAP_HFLIP |
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MDP_PIPE_CAP_VFLIP |
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0,
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},
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.lm = {
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.count = 5,
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.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
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.nb_stages = 5,
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},
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.dspp = {
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.count = 3,
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.base = { 0x04500, 0x04900, 0x04d00 },
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},
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.pp = {
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.count = 3,
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.base = { 0x21a00, 0x21b00, 0x21c00 },
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},
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.intf = {
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.base = { 0x21000, 0x21200, 0x21400, 0x21600 },
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.connect = {
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[0] = INTF_eDP,
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[1] = INTF_DSI,
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[2] = INTF_DSI,
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[3] = INTF_HDMI,
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},
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},
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.max_clk = 200000000,
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};
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const struct mdp5_cfg_hw msm8x74v2_config = {
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.name = "msm8x74",
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.mdp = {
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.count = 1,
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.caps = MDP_CAP_SMP |
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0,
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},
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.smp = {
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.mmb_count = 22,
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.mmb_size = 4096,
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.clients = {
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[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
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[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
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[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
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},
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},
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.ctl = {
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.count = 5,
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.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
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.flush_hw_mask = 0x0003ffff,
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},
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.pipe_vig = {
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.count = 3,
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.base = { 0x01100, 0x01500, 0x01900 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
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MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_rgb = {
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.count = 3,
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.base = { 0x01d00, 0x02100, 0x02500 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_dma = {
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.count = 2,
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.base = { 0x02900, 0x02d00 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
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},
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.lm = {
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.count = 5,
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.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
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.nb_stages = 5,
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.max_width = 2048,
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.max_height = 0xFFFF,
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},
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.dspp = {
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.count = 3,
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.base = { 0x04500, 0x04900, 0x04d00 },
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},
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.ad = {
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.count = 2,
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.base = { 0x13000, 0x13200 },
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},
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.pp = {
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.count = 3,
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.base = { 0x12c00, 0x12d00, 0x12e00 },
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},
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.intf = {
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.base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
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.connect = {
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[0] = INTF_eDP,
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[1] = INTF_DSI,
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[2] = INTF_DSI,
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[3] = INTF_HDMI,
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},
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},
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.max_clk = 200000000,
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};
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const struct mdp5_cfg_hw apq8084_config = {
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.name = "apq8084",
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.mdp = {
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.count = 1,
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.caps = MDP_CAP_SMP |
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0,
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},
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.smp = {
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.mmb_count = 44,
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.mmb_size = 8192,
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.clients = {
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[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
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[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
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[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
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[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
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[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
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},
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.reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
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.reserved = {
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/* Two SMP blocks are statically tied to RGB pipes: */
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[16] = 2, [17] = 2, [18] = 2, [22] = 2,
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},
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},
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.ctl = {
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.count = 5,
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.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
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.flush_hw_mask = 0x003fffff,
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},
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.pipe_vig = {
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.count = 4,
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.base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
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MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_rgb = {
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.count = 4,
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.base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_dma = {
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.count = 2,
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.base = { 0x03100, 0x03500 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
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},
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.lm = {
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.count = 6,
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.base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
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.nb_stages = 5,
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.max_width = 2048,
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.max_height = 0xFFFF,
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},
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.dspp = {
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.count = 4,
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.base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
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},
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.ad = {
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.count = 3,
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.base = { 0x13400, 0x13600, 0x13800 },
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},
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.pp = {
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.count = 4,
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.base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
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},
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.intf = {
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.base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
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.connect = {
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[0] = INTF_eDP,
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[1] = INTF_DSI,
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[2] = INTF_DSI,
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[3] = INTF_HDMI,
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},
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},
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.max_clk = 320000000,
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};
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const struct mdp5_cfg_hw msm8x16_config = {
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.name = "msm8x16",
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.mdp = {
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.count = 1,
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.base = { 0x0 },
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.caps = MDP_CAP_SMP |
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0,
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},
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.smp = {
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.mmb_count = 8,
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.mmb_size = 8192,
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.clients = {
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[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
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[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
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},
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},
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.ctl = {
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.count = 5,
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.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
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.flush_hw_mask = 0x4003ffff,
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},
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.pipe_vig = {
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.count = 1,
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.base = { 0x04000 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
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MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_rgb = {
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.count = 2,
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.base = { 0x14000, 0x16000 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_dma = {
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.count = 1,
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.base = { 0x24000 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
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},
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.lm = {
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.count = 2, /* LM0 and LM3 */
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.base = { 0x44000, 0x47000 },
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.nb_stages = 8,
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.max_width = 2048,
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.max_height = 0xFFFF,
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},
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.dspp = {
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.count = 1,
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.base = { 0x54000 },
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},
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.intf = {
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.base = { 0x00000, 0x6a800 },
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.connect = {
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[0] = INTF_DISABLED,
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[1] = INTF_DSI,
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},
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},
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.max_clk = 320000000,
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};
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const struct mdp5_cfg_hw msm8x94_config = {
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.name = "msm8x94",
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.mdp = {
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.count = 1,
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.caps = MDP_CAP_SMP |
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0,
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},
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.smp = {
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.mmb_count = 44,
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.mmb_size = 8192,
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.clients = {
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[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
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[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
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[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
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[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
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[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
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},
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.reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
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.reserved = {
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[1] = 1, [4] = 1, [7] = 1, [19] = 1,
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[16] = 5, [17] = 5, [18] = 5, [22] = 5,
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},
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},
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.ctl = {
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.count = 5,
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.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
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.flush_hw_mask = 0xf0ffffff,
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},
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.pipe_vig = {
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.count = 4,
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.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
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MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_rgb = {
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.count = 4,
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.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_dma = {
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.count = 2,
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.base = { 0x24000, 0x26000 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
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},
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.lm = {
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.count = 6,
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.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
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.nb_stages = 8,
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.max_width = 2048,
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.max_height = 0xFFFF,
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},
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.dspp = {
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.count = 4,
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.base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
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},
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.ad = {
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.count = 3,
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.base = { 0x78000, 0x78800, 0x79000 },
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},
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.pp = {
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.count = 4,
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.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
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},
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.intf = {
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.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
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.connect = {
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[0] = INTF_DISABLED,
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[1] = INTF_DSI,
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[2] = INTF_DSI,
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[3] = INTF_HDMI,
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},
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},
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.max_clk = 400000000,
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};
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const struct mdp5_cfg_hw msm8x96_config = {
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.name = "msm8x96",
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.mdp = {
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.count = 1,
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.caps = MDP_CAP_DSC |
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MDP_CAP_CDM |
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0,
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},
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.ctl = {
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.count = 5,
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.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
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.flush_hw_mask = 0xf4ffffff,
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},
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.pipe_vig = {
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.count = 4,
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.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
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.caps = MDP_PIPE_CAP_HFLIP |
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MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE |
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MDP_PIPE_CAP_CSC |
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MDP_PIPE_CAP_DECIMATION |
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MDP_PIPE_CAP_SW_PIX_EXT |
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0,
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},
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.pipe_rgb = {
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.count = 4,
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.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
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.caps = MDP_PIPE_CAP_HFLIP |
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MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE |
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MDP_PIPE_CAP_DECIMATION |
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MDP_PIPE_CAP_SW_PIX_EXT |
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0,
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},
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.pipe_dma = {
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.count = 2,
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.base = { 0x24000, 0x26000 },
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.caps = MDP_PIPE_CAP_HFLIP |
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MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SW_PIX_EXT |
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0,
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},
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.lm = {
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.count = 6,
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.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
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.nb_stages = 8,
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.max_width = 2560,
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.max_height = 0xFFFF,
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},
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.dspp = {
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.count = 2,
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.base = { 0x54000, 0x56000 },
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},
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.ad = {
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.count = 3,
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.base = { 0x78000, 0x78800, 0x79000 },
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},
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.pp = {
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.count = 4,
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.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
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},
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.cdm = {
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.count = 1,
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.base = { 0x79200 },
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},
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.dsc = {
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.count = 2,
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.base = { 0x80000, 0x80400 },
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},
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.intf = {
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.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
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.connect = {
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[0] = INTF_DISABLED,
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[1] = INTF_DSI,
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[2] = INTF_DSI,
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[3] = INTF_HDMI,
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},
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},
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.max_clk = 412500000,
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};
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static const struct mdp5_cfg_handler cfg_handlers[] = {
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{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
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{ .revision = 2, .config = { .hw = &msm8x74v2_config } },
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{ .revision = 3, .config = { .hw = &apq8084_config } },
|
|
{ .revision = 6, .config = { .hw = &msm8x16_config } },
|
|
{ .revision = 9, .config = { .hw = &msm8x94_config } },
|
|
{ .revision = 7, .config = { .hw = &msm8x96_config } },
|
|
};
|
|
|
|
static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
|
|
|
|
const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
|
|
{
|
|
return cfg_handler->config.hw;
|
|
}
|
|
|
|
struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
|
|
{
|
|
return &cfg_handler->config;
|
|
}
|
|
|
|
int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
|
|
{
|
|
return cfg_handler->revision;
|
|
}
|
|
|
|
void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
|
|
{
|
|
kfree(cfg_handler);
|
|
}
|
|
|
|
struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
|
|
uint32_t major, uint32_t minor)
|
|
{
|
|
struct drm_device *dev = mdp5_kms->dev;
|
|
struct platform_device *pdev = dev->platformdev;
|
|
struct mdp5_cfg_handler *cfg_handler;
|
|
struct mdp5_cfg_platform *pconfig;
|
|
int i, ret = 0;
|
|
|
|
cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
|
|
if (unlikely(!cfg_handler)) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
if (major != 1) {
|
|
dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
|
|
major, minor);
|
|
ret = -ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
/* only after mdp5_cfg global pointer's init can we access the hw */
|
|
for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
|
|
if (cfg_handlers[i].revision != minor)
|
|
continue;
|
|
mdp5_cfg = cfg_handlers[i].config.hw;
|
|
|
|
break;
|
|
}
|
|
if (unlikely(!mdp5_cfg)) {
|
|
dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
|
|
major, minor);
|
|
ret = -ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
cfg_handler->revision = minor;
|
|
cfg_handler->config.hw = mdp5_cfg;
|
|
|
|
pconfig = mdp5_get_config(pdev);
|
|
memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
|
|
|
|
DBG("MDP5: %s hw config selected", mdp5_cfg->name);
|
|
|
|
return cfg_handler;
|
|
|
|
fail:
|
|
if (cfg_handler)
|
|
mdp5_cfg_destroy(cfg_handler);
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
|
|
{
|
|
static struct mdp5_cfg_platform config = {};
|
|
|
|
config.iommu = iommu_domain_alloc(&platform_bus_type);
|
|
if (config.iommu) {
|
|
config.iommu->geometry.aperture_start = 0x1000;
|
|
config.iommu->geometry.aperture_end = 0xffffffff;
|
|
}
|
|
|
|
return &config;
|
|
}
|