forked from Minki/linux
bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
394 lines
9.8 KiB
C
394 lines
9.8 KiB
C
/*
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* MPC85xx setup and early boot code plus other random bits.
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/initrd.h>
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#include <linux/interrupt.h>
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#include <linux/fsl_devices.h>
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#include <linux/of_platform.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <linux/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ipic.h>
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#include <asm/pci-bridge.h>
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#include <asm/irq.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/i8259.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "mpc85xx.h"
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/*
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* The CDS board contains an FPGA/CPLD called "Cadmus", which collects
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* various logic and performs system control functions.
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* Here is the FPGA/CPLD register map.
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*/
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struct cadmus_reg {
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u8 cm_ver; /* Board version */
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u8 cm_csr; /* General control/status */
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u8 cm_rst; /* Reset control */
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u8 cm_hsclk; /* High speed clock */
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u8 cm_hsxclk; /* High speed clock extended */
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u8 cm_led; /* LED data */
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u8 cm_pci; /* PCI control/status */
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u8 cm_dma; /* DMA control */
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u8 res[248]; /* Total 256 bytes */
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};
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static struct cadmus_reg *cadmus;
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#ifdef CONFIG_PCI
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#define ARCADIA_HOST_BRIDGE_IDSEL 17
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#define ARCADIA_2ND_BRIDGE_IDSEL 3
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static int mpc85xx_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn)
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{
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/* We explicitly do not go past the Tundra 320 Bridge */
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if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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static void mpc85xx_cds_restart(char *cmd)
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{
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struct pci_dev *dev;
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u_char tmp;
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if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
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NULL))) {
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/* Use the VIA Super Southbridge to force a PCI reset */
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pci_read_config_byte(dev, 0x47, &tmp);
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pci_write_config_byte(dev, 0x47, tmp | 1);
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/* Flush the outbound PCI write queues */
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pci_read_config_byte(dev, 0x47, &tmp);
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/*
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* At this point, the harware reset should have triggered.
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* However, if it doesn't work for some mysterious reason,
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* just fall through to the default reset below.
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*/
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pci_dev_put(dev);
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}
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/*
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* If we can't find the VIA chip (maybe the P2P bridge is disabled)
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* or the VIA chip reset didn't work, just use the default reset.
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*/
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fsl_rstcr_restart(NULL);
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}
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static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
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{
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u_char c;
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if (dev->vendor == PCI_VENDOR_ID_VIA) {
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switch (dev->device) {
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case PCI_DEVICE_ID_VIA_82C586_1:
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/*
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* U-Boot does not set the enable bits
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* for the IDE device. Force them on here.
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*/
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pci_read_config_byte(dev, 0x40, &c);
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c |= 0x03; /* IDE: Chip Enable Bits */
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pci_write_config_byte(dev, 0x40, c);
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/*
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* Since only primary interface works, force the
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* IDE function to standard primary IDE interrupt
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* w/ 8259 offset
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*/
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dev->irq = 14;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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break;
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/*
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* Force legacy USB interrupt routing
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*/
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case PCI_DEVICE_ID_VIA_82C586_2:
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/* There are two USB controllers.
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* Identify them by functon number
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*/
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if (PCI_FUNC(dev->devfn) == 3)
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dev->irq = 11;
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else
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dev->irq = 10;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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default:
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break;
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}
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}
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}
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static void skip_fake_bridge(struct pci_dev *dev)
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{
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/* Make it an error to skip the fake bridge
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* in pci_setup_device() in probe.c */
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dev->hdr_type = 0x7f;
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}
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DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
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DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
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DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
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#define PCI_DEVICE_ID_IDT_TSI310 0x01a7
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/*
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* Fix Tsi310 PCI-X bridge resource.
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* Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
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* This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
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*/
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void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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struct resource *res = bus->resource[0];
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if (dev != NULL &&
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dev->vendor == PCI_VENDOR_ID_IBM &&
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dev->device == PCI_DEVICE_ID_IDT_TSI310) {
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if (res) {
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res->start = 0;
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res->end = 0x1fff;
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res->flags = IORESOURCE_IO;
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pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
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pr_info("mpc85xx_cds: %pR\n", res);
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}
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}
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fsl_pcibios_fixup_bus(bus);
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}
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#ifdef CONFIG_PPC_I8259
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static void mpc85xx_8259_cascade_handler(struct irq_desc *desc)
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{
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq != NO_IRQ)
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/* handle an interrupt from the 8259 */
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generic_handle_irq(cascade_irq);
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/* check for any interrupts from the shared IRQ line */
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handle_fasteoi_irq(desc);
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}
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static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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static struct irqaction mpc85xxcds_8259_irqaction = {
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.handler = mpc85xx_8259_cascade_action,
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.flags = IRQF_SHARED | IRQF_NO_THREAD,
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.name = "8259 cascade",
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};
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#endif /* PPC_I8259 */
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#endif /* CONFIG_PCI */
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static void __init mpc85xx_cds_pic_init(void)
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{
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struct mpic *mpic;
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mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
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static int mpc85xx_cds_8259_attach(void)
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{
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int ret;
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struct device_node *np = NULL;
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struct device_node *cascade_node = NULL;
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int cascade_irq;
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/* Initialize the i8259 controller */
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for_each_node_by_type(np, "interrupt-controller")
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if (of_device_is_compatible(np, "chrp,iic")) {
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cascade_node = np;
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break;
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}
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if (cascade_node == NULL) {
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printk(KERN_DEBUG "Could not find i8259 PIC\n");
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return -ENODEV;
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}
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cascade_irq = irq_of_parse_and_map(cascade_node, 0);
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if (cascade_irq == NO_IRQ) {
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printk(KERN_ERR "Failed to map cascade interrupt\n");
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return -ENXIO;
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}
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i8259_init(cascade_node, 0);
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of_node_put(cascade_node);
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/*
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* Hook the interrupt to make sure desc->action is never NULL.
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* This is required to ensure that the interrupt does not get
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* disabled when the last user of the shared IRQ line frees their
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* interrupt.
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*/
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if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
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printk(KERN_ERR "Failed to setup cascade interrupt\n");
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return ret;
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}
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/* Success. Connect our low-level cascade handler. */
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irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
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return 0;
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}
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machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
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#endif /* CONFIG_PPC_I8259 */
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static void mpc85xx_cds_pci_assign_primary(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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if (fsl_pci_primary)
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return;
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/*
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* MPC85xx_CDS has ISA bridge but unfortunately there is no
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* isa node in device tree. We now looking for i8259 node as
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* a workaround for such a broken device tree. This routine
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* is for complying to all device trees.
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*/
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np = of_find_node_by_name(NULL, "i8259");
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while ((fsl_pci_primary = of_get_parent(np))) {
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of_node_put(np);
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np = fsl_pci_primary;
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if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
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of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
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of_device_is_available(np))
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return;
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}
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#endif
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}
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/*
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* Setup the architecture
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*/
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static void __init mpc85xx_cds_setup_arch(void)
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{
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struct device_node *np;
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int cds_pci_slot;
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
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if (!np) {
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pr_err("Could not find FPGA node.\n");
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return;
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}
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cadmus = of_iomap(np, 0);
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of_node_put(np);
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if (!cadmus) {
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pr_err("Fail to map FPGA area.\n");
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return;
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}
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if (ppc_md.progress) {
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char buf[40];
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cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
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snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
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in_8(&cadmus->cm_ver), cds_pci_slot);
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ppc_md.progress(buf, 0);
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}
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#ifdef CONFIG_PCI
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ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#endif
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mpc85xx_cds_pci_assign_primary();
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fsl_pci_assign_primary();
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}
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static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
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in_8(&cadmus->cm_ver));
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc85xx_cds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC85xxCDS");
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}
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machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
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define_machine(mpc85xx_cds) {
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.name = "MPC85xx CDS",
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.probe = mpc85xx_cds_probe,
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.setup_arch = mpc85xx_cds_setup_arch,
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.init_IRQ = mpc85xx_cds_pic_init,
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.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
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.get_irq = mpic_get_irq,
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#ifdef CONFIG_PCI
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.restart = mpc85xx_cds_restart,
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.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#else
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.restart = fsl_rstcr_restart,
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#endif
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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