Martin Leung d5349775c1 drm/amd/display: update soc bb for nv14 ... [why] nv14 previously inherited soc bb from generic dcn 2, did not match watermark values according to memory team [how] add nv14 specific soc bb: copy nv2 generic that it was using from before, but changed num channels to 8 Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-03-09 15:06:55 -04:00
..
dcn20_dccg.c	drm/amd/display: Formula refactor for calculating DPP CLK DTO	2019-12-18 16:09:10 -05:00
dcn20_dccg.h	drm/amd/display: Revert fixup DPP programming sequence	2019-10-03 09:10:51 -05:00
dcn20_dpp_cm.c	drm/amd/display: Indirect reg read macro with shift and mask	2020-01-16 14:13:53 -05:00
dcn20_dpp.c	drm/amd/display: Double buffer dcn2 Gamut Remap	2020-01-16 14:13:30 -05:00
dcn20_dpp.h	drm/amd/display: Indirect reg read macro with shift and mask	2020-01-16 14:13:53 -05:00
dcn20_dsc.c	drm/amd/display: Initialize DSC PPS variables to 0	2020-01-09 18:07:47 -05:00
dcn20_dsc.h	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED	2019-11-13 15:29:44 -05:00
dcn20_dwb_scl.c	drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma'	2019-10-07 15:10:43 -05:00
dcn20_dwb.c
dcn20_dwb.h
dcn20_hubbub.c	drm/amd/display: Add default switch case for DCC	2020-01-16 14:15:42 -05:00
dcn20_hubbub.h	drm/amd/display: Add detile buffer size for DCN20	2019-10-03 09:10:58 -05:00
dcn20_hubp.c	drm/amd/display: Wrong ifdef guards were used around DML validation	2019-12-05 16:27:16 -05:00
dcn20_hubp.h	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_1 flag	2019-11-13 15:29:44 -05:00
dcn20_hwseq.c	drm/amd/display: Do not set optimized_require to false after plane disable	2020-02-11 12:12:31 -05:00
dcn20_hwseq.h	drm/amd/display: Add warmup escape call support	2019-12-18 16:09:09 -05:00
dcn20_init.c	drm/amd/display: add separate of private hwss functions	2019-12-05 16:26:46 -05:00
dcn20_init.h	drm/amd/display: cleanup of function pointer tables	2019-11-19 10:12:53 -05:00
dcn20_link_encoder.c	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED	2019-11-13 15:29:44 -05:00
dcn20_link_encoder.h	drm/amd/display: add missing dcn link encoder regs	2019-12-18 16:09:06 -05:00
dcn20_mmhubbub.c
dcn20_mmhubbub.h
dcn20_mpc.c	drm/amd/display: Indirect reg read macro with shift and mask	2020-01-16 14:13:53 -05:00
dcn20_mpc.h	drm/amd/display: Indirect reg read macro with shift and mask	2020-01-16 14:13:53 -05:00
dcn20_opp.c	drm/amd/display: add color space option when sending link test pattern	2019-11-19 10:12:52 -05:00
dcn20_opp.h	drm/amd/display: add color space option when sending link test pattern	2019-11-19 10:12:52 -05:00
dcn20_optc.c	drm/amd/display: Fix manual trigger source for DCN2	2019-12-18 16:09:10 -05:00
dcn20_optc.h	drm/amd/display: Fix manual trigger source for DCN2	2019-12-18 16:09:10 -05:00
dcn20_resource.c	drm/amd/display: update soc bb for nv14	2020-03-09 15:06:55 -04:00
dcn20_resource.h	drm/amd/display: MST DSC compute fair share	2020-01-09 18:07:47 -05:00
dcn20_stream_encoder.c	drm/amd/display: Reset steer fifo before unblanking the stream	2019-12-05 18:19:54 -05:00
dcn20_stream_encoder.h	drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP	2019-11-13 15:29:43 -05:00
dcn20_vmid.c	drm/amd/display: Poll for GPUVM context ready (v2)	2019-07-18 14:18:09 -05:00
dcn20_vmid.h
Makefile	amdgpu: Enable initial DCN support on POWER	2019-12-18 16:09:05 -05:00