forked from Minki/linux
e37f0d5b32
The second FlexCAN port uses different clock than the first one, configure correct clock to prevent hanging of the system during bringing up of the port. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
669 lines
17 KiB
Plaintext
669 lines
17 KiB
Plaintext
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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};
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tzic: tz-interrupt-controller@0fffc000 {
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compatible = "fsl,imx53-tzic", "fsl,tzic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x0fffc000 0x4000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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clock-frequency = <22579200>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&tzic>;
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ranges;
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ipu: ipu@18000000 {
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#crtc-cells = <1>;
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compatible = "fsl,imx53-ipu";
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reg = <0x18000000 0x080000000>;
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interrupts = <11 10>;
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};
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aips@50000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x10000000>;
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ranges;
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spba@50000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x40000>;
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ranges;
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esdhc1: esdhc@50004000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50004000 0x4000>;
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interrupts = <1>;
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clocks = <&clks 44>, <&clks 0>, <&clks 71>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc2: esdhc@50008000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50008000 0x4000>;
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interrupts = <2>;
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clocks = <&clks 45>, <&clks 0>, <&clks 72>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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uart3: serial@5000c000 {
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compatible = "fsl,imx53-uart", "fsl,imx21-uart";
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reg = <0x5000c000 0x4000>;
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interrupts = <33>;
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clocks = <&clks 32>, <&clks 33>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi1: ecspi@50010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
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reg = <0x50010000 0x4000>;
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interrupts = <36>;
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clocks = <&clks 51>, <&clks 52>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ssi2: ssi@50014000 {
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compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
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reg = <0x50014000 0x4000>;
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interrupts = <30>;
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clocks = <&clks 49>;
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fsl,fifo-depth = <15>;
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fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
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status = "disabled";
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};
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esdhc3: esdhc@50020000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50020000 0x4000>;
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interrupts = <3>;
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clocks = <&clks 46>, <&clks 0>, <&clks 73>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc4: esdhc@50024000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50024000 0x4000>;
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interrupts = <4>;
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clocks = <&clks 47>, <&clks 0>, <&clks 74>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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};
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usbotg: usb@53f80000 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80000 0x0200>;
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interrupts = <18>;
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status = "disabled";
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};
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usbh1: usb@53f80200 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80200 0x0200>;
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interrupts = <14>;
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status = "disabled";
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};
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usbh2: usb@53f80400 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80400 0x0200>;
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interrupts = <16>;
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status = "disabled";
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};
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usbh3: usb@53f80600 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80600 0x0200>;
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interrupts = <17>;
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status = "disabled";
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};
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gpio1: gpio@53f84000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f84000 0x4000>;
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interrupts = <50 51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@53f88000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f88000 0x4000>;
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interrupts = <52 53>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@53f8c000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f8c000 0x4000>;
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interrupts = <54 55>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@53f90000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f90000 0x4000>;
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interrupts = <56 57>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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wdog1: wdog@53f98000 {
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compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
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reg = <0x53f98000 0x4000>;
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interrupts = <58>;
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clocks = <&clks 0>;
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};
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wdog2: wdog@53f9c000 {
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compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
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reg = <0x53f9c000 0x4000>;
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interrupts = <59>;
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clocks = <&clks 0>;
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status = "disabled";
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};
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iomuxc: iomuxc@53fa8000 {
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compatible = "fsl,imx53-iomuxc";
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reg = <0x53fa8000 0x4000>;
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audmux {
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pinctrl_audmux_1: audmuxgrp-1 {
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fsl,pins = <
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10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
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17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
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23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
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30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
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>;
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};
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};
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fec {
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pinctrl_fec_1: fecgrp-1 {
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fsl,pins = <
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820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
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779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
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786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
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791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
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796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
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799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
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804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
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808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
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811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
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816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
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>;
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};
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};
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ecspi1 {
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pinctrl_ecspi1_1: ecspi1grp-1 {
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fsl,pins = <
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433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
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439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
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445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
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>;
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};
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};
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esdhc1 {
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pinctrl_esdhc1_1: esdhc1grp-1 {
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fsl,pins = <
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995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
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1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
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1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
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1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
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1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
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1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
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>;
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};
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pinctrl_esdhc1_2: esdhc1grp-2 {
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fsl,pins = <
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995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
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1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
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1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
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1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
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941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
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948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
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955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
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962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
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1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
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1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
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>;
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};
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};
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esdhc2 {
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pinctrl_esdhc2_1: esdhc2grp-1 {
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fsl,pins = <
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1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
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1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
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1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
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1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
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1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
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1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
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>;
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};
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};
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esdhc3 {
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pinctrl_esdhc3_1: esdhc3grp-1 {
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fsl,pins = <
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943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
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950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
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957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
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964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
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893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
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900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
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906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
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912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
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857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
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863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
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>;
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};
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};
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can1 {
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pinctrl_can1_1: can1grp-1 {
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fsl,pins = <
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847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
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853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
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>;
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};
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};
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can2 {
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pinctrl_can2_1: can2grp-1 {
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fsl,pins = <
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67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
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74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
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>;
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};
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};
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i2c1 {
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pinctrl_i2c1_1: i2c1grp-1 {
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fsl,pins = <
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333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
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341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
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>;
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};
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};
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i2c2 {
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pinctrl_i2c2_1: i2c2grp-1 {
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fsl,pins = <
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61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
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53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
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>;
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};
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};
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i2c3 {
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pinctrl_i2c3_1: i2c3grp-1 {
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fsl,pins = <
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1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
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1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
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>;
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};
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};
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
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354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
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>;
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};
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pinctrl_uart1_2: uart1grp-2 {
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fsl,pins = <
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828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
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832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
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>;
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};
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};
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uart2 {
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pinctrl_uart2_1: uart2grp-1 {
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fsl,pins = <
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841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
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836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
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>;
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};
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};
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uart3 {
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pinctrl_uart3_1: uart3grp-1 {
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fsl,pins = <
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884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
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888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
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875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
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880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
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>;
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};
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};
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uart4 {
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pinctrl_uart4_1: uart4grp-1 {
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fsl,pins = <
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11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
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18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
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>;
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};
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};
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uart5 {
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pinctrl_uart5_1: uart5grp-1 {
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fsl,pins = <
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24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
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31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
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>;
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};
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};
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};
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pwm1: pwm@53fb4000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
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reg = <0x53fb4000 0x4000>;
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clocks = <&clks 37>, <&clks 38>;
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clock-names = "ipg", "per";
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interrupts = <61>;
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};
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pwm2: pwm@53fb8000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
|
reg = <0x53fb8000 0x4000>;
|
|
clocks = <&clks 39>, <&clks 40>;
|
|
clock-names = "ipg", "per";
|
|
interrupts = <94>;
|
|
};
|
|
|
|
uart1: serial@53fbc000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x53fbc000 0x4000>;
|
|
interrupts = <31>;
|
|
clocks = <&clks 28>, <&clks 29>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@53fc0000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x53fc0000 0x4000>;
|
|
interrupts = <32>;
|
|
clocks = <&clks 30>, <&clks 31>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@53fc8000 {
|
|
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
|
reg = <0x53fc8000 0x4000>;
|
|
interrupts = <82>;
|
|
clocks = <&clks 158>, <&clks 157>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
can2: can@53fcc000 {
|
|
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
|
reg = <0x53fcc000 0x4000>;
|
|
interrupts = <83>;
|
|
clocks = <&clks 87>, <&clks 86>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
clks: ccm@53fd4000{
|
|
compatible = "fsl,imx53-ccm";
|
|
reg = <0x53fd4000 0x4000>;
|
|
interrupts = <0 71 0x04 0 72 0x04>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpio5: gpio@53fdc000 {
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fdc000 0x4000>;
|
|
interrupts = <103 104>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio@53fe0000 {
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fe0000 0x4000>;
|
|
interrupts = <105 106>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio@53fe4000 {
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fe4000 0x4000>;
|
|
interrupts = <107 108>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
i2c3: i2c@53fec000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
|
reg = <0x53fec000 0x4000>;
|
|
interrupts = <64>;
|
|
clocks = <&clks 88>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@53ff0000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x53ff0000 0x4000>;
|
|
interrupts = <13>;
|
|
clocks = <&clks 65>, <&clks 66>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
aips@60000000 { /* AIPS2 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x60000000 0x10000000>;
|
|
ranges;
|
|
|
|
uart5: serial@63f90000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x63f90000 0x4000>;
|
|
interrupts = <86>;
|
|
clocks = <&clks 67>, <&clks 68>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: ecspi@63fac000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x63fac000 0x4000>;
|
|
interrupts = <37>;
|
|
clocks = <&clks 53>, <&clks 54>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma: sdma@63fb0000 {
|
|
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
|
reg = <0x63fb0000 0x4000>;
|
|
interrupts = <6>;
|
|
clocks = <&clks 56>, <&clks 56>;
|
|
clock-names = "ipg", "ahb";
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
|
};
|
|
|
|
cspi: cspi@63fc0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
|
reg = <0x63fc0000 0x4000>;
|
|
interrupts = <38>;
|
|
clocks = <&clks 55>, <&clks 0>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@63fc4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
|
reg = <0x63fc4000 0x4000>;
|
|
interrupts = <63>;
|
|
clocks = <&clks 35>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@63fc8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
|
reg = <0x63fc8000 0x4000>;
|
|
interrupts = <62>;
|
|
clocks = <&clks 34>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi1: ssi@63fcc000 {
|
|
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
|
reg = <0x63fcc000 0x4000>;
|
|
interrupts = <29>;
|
|
clocks = <&clks 48>;
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
|
status = "disabled";
|
|
};
|
|
|
|
audmux: audmux@63fd0000 {
|
|
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
|
|
reg = <0x63fd0000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nfc: nand@63fdb000 {
|
|
compatible = "fsl,imx53-nand";
|
|
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
|
|
interrupts = <8>;
|
|
clocks = <&clks 60>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi3: ssi@63fe8000 {
|
|
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
|
reg = <0x63fe8000 0x4000>;
|
|
interrupts = <96>;
|
|
clocks = <&clks 50>;
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
|
|
status = "disabled";
|
|
};
|
|
|
|
fec: ethernet@63fec000 {
|
|
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
|
reg = <0x63fec000 0x4000>;
|
|
interrupts = <87>;
|
|
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
|
|
clock-names = "ipg", "ahb", "ptp";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|