Vincent Chen aad15bc85c riscv: Change code model of module to medany to improve data accessing ... All the loaded module locates in the region [＆_end-2G，VMALLOC_END] at runtime, so the distance from the module start to the end of the kernel image does not exceed 2GB. Hence, the code model of the kernel module can be changed to medany to improve the performance data access. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-03-03 10:27:46 -08:00
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boot	riscv: Fix gitignore	2020-02-19 16:13:51 -08:00
configs	Merge branch 'next/defconfig-add-debug' into for-next	2019-11-22 18:59:23 -08:00
include	riscv: set pmp configuration if kernel is running in M-mode	2020-02-18 09:41:24 -08:00
kernel	riscv: avoid the PIC offset of static percpu data in module beyond 2G limits	2020-03-03 10:27:45 -08:00
lib	riscv: Add KASAN support	2020-01-22 13:09:58 -08:00
mm	riscv: adjust the indent	2020-02-24 13:12:53 -08:00
net	Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next	2019-12-27 14:20:10 -08:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: mm: add support for CONFIG_DEBUG_VIRTUAL	2020-01-23 10:40:06 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: only select serial sifive if TTY is enabled	2019-12-08 20:29:01 -08:00
Makefile	riscv: Change code model of module to medany to improve data accessing	2020-03-03 10:27:46 -08:00