forked from Minki/linux
689189fb01
Convert the sh73a0 SMP code to use 32-bit PSTR access. This fixes wakeup from deep sleep for sh73a0 secondary CPUs. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
/*
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* SMP support for R-Mobile / SH-Mobile - sh73a0 portion
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 Takashi Yoshii
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/gic.h>
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#define WUPCR 0xe6151010
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#define SRESCR 0xe6151018
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#define PSTR 0xe6151040
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#define SBAR 0xe6180020
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#define APARMBAREA 0xe6f10020
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)0xf0000000;
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}
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static DEFINE_SPINLOCK(scu_lock);
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static unsigned long tmp;
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static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
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{
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void __iomem *scu_base = scu_base_addr();
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spin_lock(&scu_lock);
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tmp = __raw_readl(scu_base + 8);
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tmp &= ~clr;
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tmp |= set;
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spin_unlock(&scu_lock);
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/* disable cache coherency after releasing the lock */
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__raw_writel(tmp, scu_base + 8);
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}
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unsigned int __init sh73a0_get_core_count(void)
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{
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void __iomem *scu_base = scu_base_addr();
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#ifdef CONFIG_HAVE_ARM_TWD
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/* twd_base needs to be initialized before percpu_timer_setup() */
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twd_base = (void __iomem *)0xf0000600;
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#endif
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return scu_get_core_count(scu_base);
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}
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void __cpuinit sh73a0_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
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{
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cpu = cpu_logical_map(cpu);
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/* enable cache coherency */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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if (((__raw_readl(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
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__raw_writel(1 << cpu, __io(WUPCR)); /* wake up */
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else
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__raw_writel(1 << cpu, __io(SRESCR)); /* reset */
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return 0;
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}
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void __init sh73a0_smp_prepare_cpus(void)
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{
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int cpu = cpu_logical_map(0);
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scu_enable(scu_base_addr());
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/* Map the reset vector (in headsmp.S) */
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__raw_writel(0, __io(APARMBAREA)); /* 4k */
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__raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
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/* enable cache coherency on CPU0 */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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}
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