forked from Minki/linux
243e25112d
The XIVE interrupt controller is the new interrupt controller
found in POWER9. It supports advanced virtualization capabilities
among other things.
Currently we use a set of firmware calls that simulate the old
"XICS" interrupt controller but this is fairly inefficient.
This adds the framework for using XIVE along with a native
backend which OPAL for configuration. Later, a backend allowing
the use in a KVM or PowerVM guest will also be provided.
This disables some fast path for interrupts in KVM when XIVE is
enabled as these rely on the firmware emulation code which is no
longer available when the XIVE is used natively by Linux.
A latter patch will make KVM also directly exploit the XIVE, thus
recovering the lost performance (and more).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[mpe: Fixup pr_xxx("XIVE:"...), don't split pr_xxx() strings,
tweak Kconfig so XIVE_NATIVE selects XIVE and depends on POWERNV,
fix build errors when SMP=n, fold in fixes from Ben:
Don't call cpu_online() on an invalid CPU number
Fix irq target selection returning out of bounds cpu#
Extra sanity checks on cpu numbers
]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/*
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* Copyright 2016,2017 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __XIVE_INTERNAL_H
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#define __XIVE_INTERNAL_H
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/* Each CPU carry one of these with various per-CPU state */
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struct xive_cpu {
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#ifdef CONFIG_SMP
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/* HW irq number and data of IPI */
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u32 hw_ipi;
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struct xive_irq_data ipi_data;
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#endif /* CONFIG_SMP */
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int chip_id;
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/* Queue datas. Only one is populated */
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#define XIVE_MAX_QUEUES 8
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struct xive_q queue[XIVE_MAX_QUEUES];
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/*
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* Pending mask. Each bit corresponds to a priority that
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* potentially has pending interrupts.
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*/
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u8 pending_prio;
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/* Cache of HW CPPR */
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u8 cppr;
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};
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/* Backend ops */
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struct xive_ops {
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int (*populate_irq_data)(u32 hw_irq, struct xive_irq_data *data);
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int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*setup_cpu)(unsigned int cpu, struct xive_cpu *xc);
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void (*teardown_cpu)(unsigned int cpu, struct xive_cpu *xc);
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bool (*match)(struct device_node *np);
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void (*shutdown)(void);
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void (*update_pending)(struct xive_cpu *xc);
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void (*eoi)(u32 hw_irq);
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void (*sync_source)(u32 hw_irq);
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#ifdef CONFIG_SMP
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int (*get_ipi)(unsigned int cpu, struct xive_cpu *xc);
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void (*put_ipi)(unsigned int cpu, struct xive_cpu *xc);
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#endif
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const char *name;
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};
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bool xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
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u8 max_prio);
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extern bool xive_cmdline_disabled;
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#endif /* __XIVE_INTERNAL_H */
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