forked from Minki/linux
a98f26f183
In order to make the number of interrupts configurable, use the new fancy device management API to add KVM_DEV_ARM_VGIC_GRP_NR_IRQS as a VGIC configurable attribute. Userspace can now specify the exact size of the GIC (by increments of 32 interrupts). Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
84 lines
3.4 KiB
Plaintext
84 lines
3.4 KiB
Plaintext
ARM Virtual Generic Interrupt Controller (VGIC)
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===============================================
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Device types supported:
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KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
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Only one VGIC instance may be instantiated through either this API or the
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legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt
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controller, requiring emulated user-space devices to inject interrupts to the
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VGIC instead of directly to CPUs.
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Groups:
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KVM_DEV_ARM_VGIC_GRP_ADDR
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Attributes:
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KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
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Base address in the guest physical address space of the GIC distributor
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register mappings.
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KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
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Base address in the guest physical address space of the GIC virtual cpu
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interface register mappings.
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KVM_DEV_ARM_VGIC_GRP_DIST_REGS
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Attributes:
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The attr field of kvm_device_attr encodes two values:
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bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
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values: | reserved | cpu id | offset |
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All distributor regs are (rw, 32-bit)
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The offset is relative to the "Distributor base address" as defined in the
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GICv2 specs. Getting or setting such a register has the same effect as
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reading or writing the register on the actual hardware from the cpu
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specified with cpu id field. Note that most distributor fields are not
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banked, but return the same value regardless of the cpu id used to access
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the register.
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Limitations:
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- Priorities are not implemented, and registers are RAZ/WI
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Errors:
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-ENODEV: Getting or setting this register is not yet supported
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-EBUSY: One or more VCPUs are running
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KVM_DEV_ARM_VGIC_GRP_CPU_REGS
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Attributes:
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The attr field of kvm_device_attr encodes two values:
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bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
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values: | reserved | cpu id | offset |
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All CPU interface regs are (rw, 32-bit)
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The offset specifies the offset from the "CPU interface base address" as
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defined in the GICv2 specs. Getting or setting such a register has the
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same effect as reading or writing the register on the actual hardware.
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The Active Priorities Registers APRn are implementation defined, so we set a
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fixed format for our implementation that fits with the model of a "GICv2
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implementation without the security extensions" which we present to the
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guest. This interface always exposes four register APR[0-3] describing the
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maximum possible 128 preemption levels. The semantics of the register
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indicate if any interrupts in a given preemption level are in the active
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state by setting the corresponding bit.
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Thus, preemption level X has one or more active interrupts if and only if:
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APRn[X mod 32] == 0b1, where n = X / 32
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Bits for undefined preemption levels are RAZ/WI.
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Limitations:
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- Priorities are not implemented, and registers are RAZ/WI
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Errors:
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-ENODEV: Getting or setting this register is not yet supported
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-EBUSY: One or more VCPUs are running
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KVM_DEV_ARM_VGIC_GRP_NR_IRQS
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Attributes:
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A value describing the number of interrupts (SGI, PPI and SPI) for
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this GIC instance, ranging from 64 to 1024, in increments of 32.
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Errors:
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-EINVAL: Value set is out of the expected range
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-EBUSY: Value has already be set, or GIC has already been initialized
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with default values.
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