forked from Minki/linux
a8edc3bf05
To allow for usage of the flow steering Firmware structures in more locations over the driver, such as the resource tracker, move them from mcg.c to common header files. Signed-off-by: Hadar Hen Zion <hadarh@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1196 lines
32 KiB
C
1196 lines
32 KiB
C
/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
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* Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
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* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX4_H
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#define MLX4_H
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#include <linux/mutex.h>
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#include <linux/radix-tree.h>
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#include <linux/rbtree.h>
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#include <linux/timer.h>
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#include <linux/semaphore.h>
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#include <linux/workqueue.h>
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#include <linux/mlx4/device.h>
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#include <linux/mlx4/driver.h>
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#include <linux/mlx4/doorbell.h>
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#include <linux/mlx4/cmd.h>
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#define DRV_NAME "mlx4_core"
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#define PFX DRV_NAME ": "
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#define DRV_VERSION "1.1"
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#define DRV_RELDATE "Dec, 2011"
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#define MLX4_FS_UDP_UC_EN (1 << 1)
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#define MLX4_FS_TCP_UC_EN (1 << 2)
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#define MLX4_FS_NUM_OF_L2_ADDR 8
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#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
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#define MLX4_FS_NUM_MCG (1 << 17)
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enum {
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MLX4_FS_L2_HASH = 0,
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MLX4_FS_L2_L3_L4_HASH,
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};
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#define MLX4_NUM_UP 8
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#define MLX4_NUM_TC 8
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#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
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#define MLX4_RATELIMIT_DEFAULT 0xffff
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struct mlx4_set_port_prio2tc_context {
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u8 prio2tc[4];
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};
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struct mlx4_port_scheduler_tc_cfg_be {
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__be16 pg;
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__be16 bw_precentage;
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__be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
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__be16 max_bw_value;
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};
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struct mlx4_set_port_scheduler_context {
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struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
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};
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enum {
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MLX4_HCR_BASE = 0x80680,
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MLX4_HCR_SIZE = 0x0001c,
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MLX4_CLR_INT_SIZE = 0x00008,
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MLX4_SLAVE_COMM_BASE = 0x0,
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MLX4_COMM_PAGESIZE = 0x1000
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};
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enum {
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MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
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MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
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MLX4_MTT_ENTRY_PER_SEG = 8,
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};
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enum {
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MLX4_NUM_PDS = 1 << 15
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};
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enum {
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MLX4_CMPT_TYPE_QP = 0,
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MLX4_CMPT_TYPE_SRQ = 1,
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MLX4_CMPT_TYPE_CQ = 2,
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MLX4_CMPT_TYPE_EQ = 3,
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MLX4_CMPT_NUM_TYPE
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};
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enum {
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MLX4_CMPT_SHIFT = 24,
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MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
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};
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enum mlx4_mr_state {
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MLX4_MR_DISABLED = 0,
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MLX4_MR_EN_HW,
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MLX4_MR_EN_SW
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};
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#define MLX4_COMM_TIME 10000
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enum {
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MLX4_COMM_CMD_RESET,
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MLX4_COMM_CMD_VHCR0,
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MLX4_COMM_CMD_VHCR1,
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MLX4_COMM_CMD_VHCR2,
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MLX4_COMM_CMD_VHCR_EN,
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MLX4_COMM_CMD_VHCR_POST,
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MLX4_COMM_CMD_FLR = 254
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};
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/*The flag indicates that the slave should delay the RESET cmd*/
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#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
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/*indicates how many retries will be done if we are in the middle of FLR*/
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#define NUM_OF_RESET_RETRIES 10
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#define SLEEP_TIME_IN_RESET (2 * 1000)
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enum mlx4_resource {
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RES_QP,
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RES_CQ,
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RES_SRQ,
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RES_XRCD,
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RES_MPT,
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RES_MTT,
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RES_MAC,
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RES_VLAN,
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RES_EQ,
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RES_COUNTER,
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RES_FS_RULE,
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MLX4_NUM_OF_RESOURCE_TYPE
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};
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enum mlx4_alloc_mode {
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RES_OP_RESERVE,
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RES_OP_RESERVE_AND_MAP,
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RES_OP_MAP_ICM,
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};
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enum mlx4_res_tracker_free_type {
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RES_TR_FREE_ALL,
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RES_TR_FREE_SLAVES_ONLY,
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RES_TR_FREE_STRUCTS_ONLY,
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};
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/*
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*Virtual HCR structures.
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* mlx4_vhcr is the sw representation, in machine endianess
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*
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* mlx4_vhcr_cmd is the formalized structure, the one that is passed
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* to FW to go through communication channel.
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* It is big endian, and has the same structure as the physical HCR
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* used by command interface
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*/
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struct mlx4_vhcr {
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u64 in_param;
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u64 out_param;
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u32 in_modifier;
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u32 errno;
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u16 op;
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u16 token;
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u8 op_modifier;
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u8 e_bit;
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};
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struct mlx4_vhcr_cmd {
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__be64 in_param;
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__be32 in_modifier;
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__be64 out_param;
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__be16 token;
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u16 reserved;
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u8 status;
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u8 flags;
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__be16 opcode;
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};
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struct mlx4_cmd_info {
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u16 opcode;
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bool has_inbox;
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bool has_outbox;
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bool out_is_imm;
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bool encode_slave_id;
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int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox);
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int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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};
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#ifdef CONFIG_MLX4_DEBUG
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extern int mlx4_debug_level;
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#else /* CONFIG_MLX4_DEBUG */
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#define mlx4_debug_level (0)
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#endif /* CONFIG_MLX4_DEBUG */
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#define mlx4_dbg(mdev, format, arg...) \
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do { \
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if (mlx4_debug_level) \
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dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
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} while (0)
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#define mlx4_err(mdev, format, arg...) \
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dev_err(&mdev->pdev->dev, format, ##arg)
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#define mlx4_info(mdev, format, arg...) \
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dev_info(&mdev->pdev->dev, format, ##arg)
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#define mlx4_warn(mdev, format, arg...) \
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dev_warn(&mdev->pdev->dev, format, ##arg)
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extern int mlx4_log_num_mgm_entry_size;
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extern int log_mtts_per_seg;
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#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
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#define ALL_SLAVES 0xff
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struct mlx4_bitmap {
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u32 last;
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u32 top;
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u32 max;
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u32 reserved_top;
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u32 mask;
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u32 avail;
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spinlock_t lock;
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unsigned long *table;
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};
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struct mlx4_buddy {
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unsigned long **bits;
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unsigned int *num_free;
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u32 max_order;
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spinlock_t lock;
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};
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struct mlx4_icm;
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struct mlx4_icm_table {
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u64 virt;
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int num_icm;
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u32 num_obj;
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int obj_size;
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int lowmem;
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int coherent;
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struct mutex mutex;
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struct mlx4_icm **icm;
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};
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/*
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* Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
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*/
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struct mlx4_mpt_entry {
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__be32 flags;
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__be32 qpn;
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__be32 key;
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__be32 pd_flags;
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__be64 start;
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__be64 length;
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__be32 lkey;
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__be32 win_cnt;
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u8 reserved1[3];
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u8 mtt_rep;
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__be64 mtt_addr;
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__be32 mtt_sz;
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__be32 entity_size;
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__be32 first_byte_offset;
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} __packed;
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/*
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* Must be packed because start is 64 bits but only aligned to 32 bits.
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*/
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struct mlx4_eq_context {
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__be32 flags;
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u16 reserved1[3];
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__be16 page_offset;
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u8 log_eq_size;
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u8 reserved2[4];
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u8 eq_period;
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u8 reserved3;
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u8 eq_max_count;
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u8 reserved4[3];
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u8 intr;
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u8 log_page_size;
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u8 reserved5[2];
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u8 mtt_base_addr_h;
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__be32 mtt_base_addr_l;
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u32 reserved6[2];
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__be32 consumer_index;
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__be32 producer_index;
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u32 reserved7[4];
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};
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struct mlx4_cq_context {
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__be32 flags;
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u16 reserved1[3];
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__be16 page_offset;
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__be32 logsize_usrpage;
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__be16 cq_period;
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__be16 cq_max_count;
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u8 reserved2[3];
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u8 comp_eqn;
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u8 log_page_size;
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u8 reserved3[2];
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u8 mtt_base_addr_h;
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__be32 mtt_base_addr_l;
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__be32 last_notified_index;
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__be32 solicit_producer_index;
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__be32 consumer_index;
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__be32 producer_index;
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u32 reserved4[2];
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__be64 db_rec_addr;
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};
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struct mlx4_srq_context {
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__be32 state_logsize_srqn;
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u8 logstride;
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u8 reserved1;
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__be16 xrcd;
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__be32 pg_offset_cqn;
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u32 reserved2;
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u8 log_page_size;
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u8 reserved3[2];
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u8 mtt_base_addr_h;
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__be32 mtt_base_addr_l;
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__be32 pd;
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__be16 limit_watermark;
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__be16 wqe_cnt;
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u16 reserved4;
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__be16 wqe_counter;
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u32 reserved5;
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__be64 db_rec_addr;
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};
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struct mlx4_eq {
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struct mlx4_dev *dev;
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void __iomem *doorbell;
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int eqn;
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u32 cons_index;
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u16 irq;
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u16 have_irq;
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int nent;
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struct mlx4_buf_list *page_list;
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struct mlx4_mtt mtt;
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};
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struct mlx4_slave_eqe {
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u8 type;
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u8 port;
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u32 param;
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};
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struct mlx4_slave_event_eq_info {
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int eqn;
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u16 token;
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};
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struct mlx4_profile {
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int num_qp;
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int rdmarc_per_qp;
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int num_srq;
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int num_cq;
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int num_mcg;
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int num_mpt;
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unsigned num_mtt;
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};
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struct mlx4_fw {
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u64 clr_int_base;
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u64 catas_offset;
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u64 comm_base;
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struct mlx4_icm *fw_icm;
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struct mlx4_icm *aux_icm;
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u32 catas_size;
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u16 fw_pages;
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u8 clr_int_bar;
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u8 catas_bar;
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u8 comm_bar;
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};
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struct mlx4_comm {
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u32 slave_write;
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u32 slave_read;
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};
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enum {
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MLX4_MCAST_CONFIG = 0,
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MLX4_MCAST_DISABLE = 1,
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MLX4_MCAST_ENABLE = 2,
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};
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#define VLAN_FLTR_SIZE 128
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struct mlx4_vlan_fltr {
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__be32 entry[VLAN_FLTR_SIZE];
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};
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struct mlx4_mcast_entry {
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struct list_head list;
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u64 addr;
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};
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struct mlx4_promisc_qp {
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struct list_head list;
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u32 qpn;
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};
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struct mlx4_steer_index {
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struct list_head list;
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unsigned int index;
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struct list_head duplicates;
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};
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#define MLX4_EVENT_TYPES_NUM 64
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struct mlx4_slave_state {
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u8 comm_toggle;
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u8 last_cmd;
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u8 init_port_mask;
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bool active;
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u8 function;
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dma_addr_t vhcr_dma;
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u16 mtu[MLX4_MAX_PORTS + 1];
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__be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
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struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
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struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
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struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
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/* event type to eq number lookup */
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struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
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u16 eq_pi;
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u16 eq_ci;
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spinlock_t lock;
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/*initialized via the kzalloc*/
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u8 is_slave_going_down;
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u32 cookie;
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};
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struct slave_list {
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struct mutex mutex;
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struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
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};
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struct mlx4_resource_tracker {
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spinlock_t lock;
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/* tree for each resources */
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struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
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/* num_of_slave's lists, one per slave */
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struct slave_list *slave_list;
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};
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#define SLAVE_EVENT_EQ_SIZE 128
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struct mlx4_slave_event_eq {
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u32 eqn;
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u32 cons;
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u32 prod;
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struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
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};
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struct mlx4_master_qp0_state {
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int proxy_qp0_active;
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int qp0_active;
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int port_active;
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};
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struct mlx4_mfunc_master_ctx {
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struct mlx4_slave_state *slave_state;
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struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
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int init_port_ref[MLX4_MAX_PORTS + 1];
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u16 max_mtu[MLX4_MAX_PORTS + 1];
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int disable_mcast_ref[MLX4_MAX_PORTS + 1];
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struct mlx4_resource_tracker res_tracker;
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struct workqueue_struct *comm_wq;
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struct work_struct comm_work;
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struct work_struct slave_event_work;
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struct work_struct slave_flr_event_work;
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spinlock_t slave_state_lock;
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__be32 comm_arm_bit_vector[4];
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struct mlx4_eqe cmd_eqe;
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struct mlx4_slave_event_eq slave_eq;
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struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
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};
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struct mlx4_mfunc {
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struct mlx4_comm __iomem *comm;
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struct mlx4_vhcr_cmd *vhcr;
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dma_addr_t vhcr_dma;
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struct mlx4_mfunc_master_ctx master;
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};
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struct mlx4_cmd {
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struct pci_pool *pool;
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void __iomem *hcr;
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struct mutex hcr_mutex;
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struct semaphore poll_sem;
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|
struct semaphore event_sem;
|
|
struct semaphore slave_sem;
|
|
int max_cmds;
|
|
spinlock_t context_lock;
|
|
int free_head;
|
|
struct mlx4_cmd_context *context;
|
|
u16 token_mask;
|
|
u8 use_events;
|
|
u8 toggle;
|
|
u8 comm_toggle;
|
|
};
|
|
|
|
struct mlx4_uar_table {
|
|
struct mlx4_bitmap bitmap;
|
|
};
|
|
|
|
struct mlx4_mr_table {
|
|
struct mlx4_bitmap mpt_bitmap;
|
|
struct mlx4_buddy mtt_buddy;
|
|
u64 mtt_base;
|
|
u64 mpt_base;
|
|
struct mlx4_icm_table mtt_table;
|
|
struct mlx4_icm_table dmpt_table;
|
|
};
|
|
|
|
struct mlx4_cq_table {
|
|
struct mlx4_bitmap bitmap;
|
|
spinlock_t lock;
|
|
struct radix_tree_root tree;
|
|
struct mlx4_icm_table table;
|
|
struct mlx4_icm_table cmpt_table;
|
|
};
|
|
|
|
struct mlx4_eq_table {
|
|
struct mlx4_bitmap bitmap;
|
|
char *irq_names;
|
|
void __iomem *clr_int;
|
|
void __iomem **uar_map;
|
|
u32 clr_mask;
|
|
struct mlx4_eq *eq;
|
|
struct mlx4_icm_table table;
|
|
struct mlx4_icm_table cmpt_table;
|
|
int have_irq;
|
|
u8 inta_pin;
|
|
};
|
|
|
|
struct mlx4_srq_table {
|
|
struct mlx4_bitmap bitmap;
|
|
spinlock_t lock;
|
|
struct radix_tree_root tree;
|
|
struct mlx4_icm_table table;
|
|
struct mlx4_icm_table cmpt_table;
|
|
};
|
|
|
|
struct mlx4_qp_table {
|
|
struct mlx4_bitmap bitmap;
|
|
u32 rdmarc_base;
|
|
int rdmarc_shift;
|
|
spinlock_t lock;
|
|
struct mlx4_icm_table qp_table;
|
|
struct mlx4_icm_table auxc_table;
|
|
struct mlx4_icm_table altc_table;
|
|
struct mlx4_icm_table rdmarc_table;
|
|
struct mlx4_icm_table cmpt_table;
|
|
};
|
|
|
|
struct mlx4_mcg_table {
|
|
struct mutex mutex;
|
|
struct mlx4_bitmap bitmap;
|
|
struct mlx4_icm_table table;
|
|
};
|
|
|
|
struct mlx4_catas_err {
|
|
u32 __iomem *map;
|
|
struct timer_list timer;
|
|
struct list_head list;
|
|
};
|
|
|
|
#define MLX4_MAX_MAC_NUM 128
|
|
#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
|
|
|
|
struct mlx4_mac_table {
|
|
__be64 entries[MLX4_MAX_MAC_NUM];
|
|
int refs[MLX4_MAX_MAC_NUM];
|
|
struct mutex mutex;
|
|
int total;
|
|
int max;
|
|
};
|
|
|
|
#define MLX4_MAX_VLAN_NUM 128
|
|
#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
|
|
|
|
struct mlx4_vlan_table {
|
|
__be32 entries[MLX4_MAX_VLAN_NUM];
|
|
int refs[MLX4_MAX_VLAN_NUM];
|
|
struct mutex mutex;
|
|
int total;
|
|
int max;
|
|
};
|
|
|
|
#define SET_PORT_GEN_ALL_VALID 0x7
|
|
#define SET_PORT_PROMISC_SHIFT 31
|
|
#define SET_PORT_MC_PROMISC_SHIFT 30
|
|
|
|
enum {
|
|
MCAST_DIRECT_ONLY = 0,
|
|
MCAST_DIRECT = 1,
|
|
MCAST_DEFAULT = 2
|
|
};
|
|
|
|
|
|
struct mlx4_set_port_general_context {
|
|
u8 reserved[3];
|
|
u8 flags;
|
|
u16 reserved2;
|
|
__be16 mtu;
|
|
u8 pptx;
|
|
u8 pfctx;
|
|
u16 reserved3;
|
|
u8 pprx;
|
|
u8 pfcrx;
|
|
u16 reserved4;
|
|
};
|
|
|
|
struct mlx4_set_port_rqp_calc_context {
|
|
__be32 base_qpn;
|
|
u8 rererved;
|
|
u8 n_mac;
|
|
u8 n_vlan;
|
|
u8 n_prio;
|
|
u8 reserved2[3];
|
|
u8 mac_miss;
|
|
u8 intra_no_vlan;
|
|
u8 no_vlan;
|
|
u8 intra_vlan_miss;
|
|
u8 vlan_miss;
|
|
u8 reserved3[3];
|
|
u8 no_vlan_prio;
|
|
__be32 promisc;
|
|
__be32 mcast;
|
|
};
|
|
|
|
struct mlx4_mac_entry {
|
|
u64 mac;
|
|
u64 reg_id;
|
|
};
|
|
|
|
struct mlx4_port_info {
|
|
struct mlx4_dev *dev;
|
|
int port;
|
|
char dev_name[16];
|
|
struct device_attribute port_attr;
|
|
enum mlx4_port_type tmp_type;
|
|
char dev_mtu_name[16];
|
|
struct device_attribute port_mtu_attr;
|
|
struct mlx4_mac_table mac_table;
|
|
struct radix_tree_root mac_tree;
|
|
struct mlx4_vlan_table vlan_table;
|
|
int base_qpn;
|
|
};
|
|
|
|
struct mlx4_sense {
|
|
struct mlx4_dev *dev;
|
|
u8 do_sense_port[MLX4_MAX_PORTS + 1];
|
|
u8 sense_allowed[MLX4_MAX_PORTS + 1];
|
|
struct delayed_work sense_poll;
|
|
};
|
|
|
|
struct mlx4_msix_ctl {
|
|
u64 pool_bm;
|
|
struct mutex pool_lock;
|
|
};
|
|
|
|
struct mlx4_steer {
|
|
struct list_head promisc_qps[MLX4_NUM_STEERS];
|
|
struct list_head steer_entries[MLX4_NUM_STEERS];
|
|
};
|
|
|
|
struct mlx4_net_trans_rule_hw_ctrl {
|
|
__be32 ctrl;
|
|
__be32 vf_vep_port;
|
|
__be32 qpn;
|
|
__be32 reserved;
|
|
};
|
|
|
|
struct mlx4_net_trans_rule_hw_ib {
|
|
u8 size;
|
|
u8 rsvd1;
|
|
__be16 id;
|
|
u32 rsvd2;
|
|
__be32 qpn;
|
|
__be32 qpn_mask;
|
|
u8 dst_gid[16];
|
|
u8 dst_gid_msk[16];
|
|
} __packed;
|
|
|
|
struct mlx4_net_trans_rule_hw_eth {
|
|
u8 size;
|
|
u8 rsvd;
|
|
__be16 id;
|
|
u8 rsvd1[6];
|
|
u8 dst_mac[6];
|
|
u16 rsvd2;
|
|
u8 dst_mac_msk[6];
|
|
u16 rsvd3;
|
|
u8 src_mac[6];
|
|
u16 rsvd4;
|
|
u8 src_mac_msk[6];
|
|
u8 rsvd5;
|
|
u8 ether_type_enable;
|
|
__be16 ether_type;
|
|
__be16 vlan_id_msk;
|
|
__be16 vlan_id;
|
|
} __packed;
|
|
|
|
struct mlx4_net_trans_rule_hw_tcp_udp {
|
|
u8 size;
|
|
u8 rsvd;
|
|
__be16 id;
|
|
__be16 rsvd1[3];
|
|
__be16 dst_port;
|
|
__be16 rsvd2;
|
|
__be16 dst_port_msk;
|
|
__be16 rsvd3;
|
|
__be16 src_port;
|
|
__be16 rsvd4;
|
|
__be16 src_port_msk;
|
|
} __packed;
|
|
|
|
struct mlx4_net_trans_rule_hw_ipv4 {
|
|
u8 size;
|
|
u8 rsvd;
|
|
__be16 id;
|
|
__be32 rsvd1;
|
|
__be32 dst_ip;
|
|
__be32 dst_ip_msk;
|
|
__be32 src_ip;
|
|
__be32 src_ip_msk;
|
|
} __packed;
|
|
|
|
struct _rule_hw {
|
|
union {
|
|
struct {
|
|
u8 size;
|
|
u8 rsvd;
|
|
__be16 id;
|
|
};
|
|
struct mlx4_net_trans_rule_hw_eth eth;
|
|
struct mlx4_net_trans_rule_hw_ib ib;
|
|
struct mlx4_net_trans_rule_hw_ipv4 ipv4;
|
|
struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
|
|
};
|
|
};
|
|
|
|
struct mlx4_priv {
|
|
struct mlx4_dev dev;
|
|
|
|
struct list_head dev_list;
|
|
struct list_head ctx_list;
|
|
spinlock_t ctx_lock;
|
|
|
|
struct list_head pgdir_list;
|
|
struct mutex pgdir_mutex;
|
|
|
|
struct mlx4_fw fw;
|
|
struct mlx4_cmd cmd;
|
|
struct mlx4_mfunc mfunc;
|
|
|
|
struct mlx4_bitmap pd_bitmap;
|
|
struct mlx4_bitmap xrcd_bitmap;
|
|
struct mlx4_uar_table uar_table;
|
|
struct mlx4_mr_table mr_table;
|
|
struct mlx4_cq_table cq_table;
|
|
struct mlx4_eq_table eq_table;
|
|
struct mlx4_srq_table srq_table;
|
|
struct mlx4_qp_table qp_table;
|
|
struct mlx4_mcg_table mcg_table;
|
|
struct mlx4_bitmap counters_bitmap;
|
|
|
|
struct mlx4_catas_err catas_err;
|
|
|
|
void __iomem *clr_base;
|
|
|
|
struct mlx4_uar driver_uar;
|
|
void __iomem *kar;
|
|
struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
|
|
struct mlx4_sense sense;
|
|
struct mutex port_mutex;
|
|
struct mlx4_msix_ctl msix_ctl;
|
|
struct mlx4_steer *steer;
|
|
struct list_head bf_list;
|
|
struct mutex bf_mutex;
|
|
struct io_mapping *bf_mapping;
|
|
int reserved_mtts;
|
|
int fs_hash_mode;
|
|
};
|
|
|
|
static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
|
|
{
|
|
return container_of(dev, struct mlx4_priv, dev);
|
|
}
|
|
|
|
#define MLX4_SENSE_RANGE (HZ * 3)
|
|
|
|
extern struct workqueue_struct *mlx4_wq;
|
|
|
|
u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
|
|
void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
|
|
u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
|
|
void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
|
|
u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
|
|
int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
|
|
u32 reserved_bot, u32 resetrved_top);
|
|
void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
|
|
|
|
int mlx4_reset(struct mlx4_dev *dev);
|
|
|
|
int mlx4_alloc_eq_table(struct mlx4_dev *dev);
|
|
void mlx4_free_eq_table(struct mlx4_dev *dev);
|
|
|
|
int mlx4_init_pd_table(struct mlx4_dev *dev);
|
|
int mlx4_init_xrcd_table(struct mlx4_dev *dev);
|
|
int mlx4_init_uar_table(struct mlx4_dev *dev);
|
|
int mlx4_init_mr_table(struct mlx4_dev *dev);
|
|
int mlx4_init_eq_table(struct mlx4_dev *dev);
|
|
int mlx4_init_cq_table(struct mlx4_dev *dev);
|
|
int mlx4_init_qp_table(struct mlx4_dev *dev);
|
|
int mlx4_init_srq_table(struct mlx4_dev *dev);
|
|
int mlx4_init_mcg_table(struct mlx4_dev *dev);
|
|
|
|
void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
|
|
void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
|
|
int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
|
|
void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
|
|
int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
|
|
void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
|
|
int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
|
|
void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
|
|
int __mlx4_mr_reserve(struct mlx4_dev *dev);
|
|
void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
|
|
int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
|
|
void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
|
|
u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
|
|
void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
|
|
|
|
int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
|
|
int *base);
|
|
void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
|
|
int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
|
|
void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
|
|
int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
|
|
int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
|
|
int start_index, int npages, u64 *page_list);
|
|
int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
|
|
void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
|
|
int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
|
|
void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
|
|
|
|
void mlx4_start_catas_poll(struct mlx4_dev *dev);
|
|
void mlx4_stop_catas_poll(struct mlx4_dev *dev);
|
|
void mlx4_catas_init(void);
|
|
int mlx4_restart_one(struct pci_dev *pdev);
|
|
int mlx4_register_device(struct mlx4_dev *dev);
|
|
void mlx4_unregister_device(struct mlx4_dev *dev);
|
|
void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
|
|
unsigned long param);
|
|
|
|
struct mlx4_dev_cap;
|
|
struct mlx4_init_hca_param;
|
|
|
|
u64 mlx4_make_profile(struct mlx4_dev *dev,
|
|
struct mlx4_profile *request,
|
|
struct mlx4_dev_cap *dev_cap,
|
|
struct mlx4_init_hca_param *init_hca);
|
|
void mlx4_master_comm_channel(struct work_struct *work);
|
|
void mlx4_gen_slave_eqe(struct work_struct *work);
|
|
void mlx4_master_handle_slave_flr(struct work_struct *work);
|
|
|
|
int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
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int mlx4_cmd_init(struct mlx4_dev *dev);
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void mlx4_cmd_cleanup(struct mlx4_dev *dev);
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int mlx4_multi_func_init(struct mlx4_dev *dev);
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void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
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void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
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int mlx4_cmd_use_events(struct mlx4_dev *dev);
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void mlx4_cmd_use_polling(struct mlx4_dev *dev);
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int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
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unsigned long timeout);
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void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
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void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
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void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
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void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
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void mlx4_handle_catas_err(struct mlx4_dev *dev);
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int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
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enum mlx4_port_type *type);
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void mlx4_do_sense_ports(struct mlx4_dev *dev,
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enum mlx4_port_type *stype,
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enum mlx4_port_type *defaults);
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void mlx4_start_sense(struct mlx4_dev *dev);
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void mlx4_stop_sense(struct mlx4_dev *dev);
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void mlx4_sense_init(struct mlx4_dev *dev);
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int mlx4_check_port_params(struct mlx4_dev *dev,
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enum mlx4_port_type *port_type);
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int mlx4_change_port_types(struct mlx4_dev *dev,
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enum mlx4_port_type *port_types);
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void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
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void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
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int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
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/* resource tracker functions*/
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int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
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enum mlx4_resource resource_type,
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u64 resource_id, int *slave);
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void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
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int mlx4_init_resource_tracker(struct mlx4_dev *dev);
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|
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void mlx4_free_resource_tracker(struct mlx4_dev *dev,
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enum mlx4_res_tracker_free_type type);
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|
|
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int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
|
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struct mlx4_cmd_info *cmd);
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int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
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|
|
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int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
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int *gid_tbl_len, int *pkey_tbl_len);
|
|
|
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int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
|
|
int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
|
|
enum mlx4_protocol prot, enum mlx4_steer_type steer);
|
|
int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
|
|
int block_mcast_loopback, enum mlx4_protocol prot,
|
|
enum mlx4_steer_type steer);
|
|
int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
|
|
int port, void *buf);
|
|
int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
|
|
struct mlx4_cmd_mailbox *outbox);
|
|
int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
|
|
struct mlx4_vhcr *vhcr,
|
|
struct mlx4_cmd_mailbox *inbox,
|
|
struct mlx4_cmd_mailbox *outbox,
|
|
struct mlx4_cmd_info *cmd);
|
|
|
|
int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
|
|
int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
|
|
|
|
static inline void set_param_l(u64 *arg, u32 val)
|
|
{
|
|
*((u32 *)arg) = val;
|
|
}
|
|
|
|
static inline void set_param_h(u64 *arg, u32 val)
|
|
{
|
|
*arg = (*arg & 0xffffffff) | ((u64) val << 32);
|
|
}
|
|
|
|
static inline u32 get_param_l(u64 *arg)
|
|
{
|
|
return (u32) (*arg & 0xffffffff);
|
|
}
|
|
|
|
static inline u32 get_param_h(u64 *arg)
|
|
{
|
|
return (u32)(*arg >> 32);
|
|
}
|
|
|
|
static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
|
|
{
|
|
return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
|
|
}
|
|
|
|
#define NOT_MASKED_PD_BITS 17
|
|
|
|
#endif /* MLX4_H */
|