forked from Minki/linux
a8db8cf0d8
Each revmap type has different arguments for setting up the revmap.
This patch splits up the generator functions so that each revmap type
can do its own setup and the user doesn't need to keep track of how
each revmap type handles the arguments.
This patch also adds a host_data argument to the generators. There are
cases where the host_data pointer will be needed before the function returns.
ie. the legacy map calls the .map callback for each irq before returning.
v2: - Add void *host_data argument to irq_domain_add_*() functions
- fixed failure to compile
- Moved IRQ_DOMAIN_MAP_* defines into irqdomain.c
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Milton Miller <miltonm@bga.com>
Tested-by: Olof Johansson <olof@lixom.net>
441 lines
11 KiB
C
441 lines
11 KiB
C
/*
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* Common routines for Tundra Semiconductor TSI108 host bridge.
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*
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* 2004-2005 (c) Tundra Semiconductor Corp.
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* Author: Alex Bounine (alexandreb@tundra.com)
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* Author: Roy Zang (tie-fei.zang@freescale.com)
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* Add pci interrupt router host
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/tsi108.h>
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#include <asm/tsi108_pci.h>
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#include <asm/tsi108_irq.h>
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#include <asm/prom.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define tsi_mk_config_addr(bus, devfunc, offset) \
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((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
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u32 tsi108_pci_cfg_base;
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static u32 tsi108_pci_cfg_phys;
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u32 tsi108_csr_vir_base;
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static struct irq_domain *pci_irq_host;
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extern u32 get_vir_csrbase(void);
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extern u32 tsi108_read_reg(u32 reg_offset);
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extern void tsi108_write_reg(u32 reg_offset, u32 val);
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int
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tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
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int offset, int len, u32 val)
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{
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volatile unsigned char *cfg_addr;
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struct pci_controller *hose = pci_bus_to_host(bus);
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfunc))
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return PCIBIOS_DEVICE_NOT_FOUND;
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cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
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devfunc, offset) |
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(offset & 0x03));
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#ifdef DEBUG
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printk("PCI CFG write : ");
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printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
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printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
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printk("data = 0x%08x\n", val);
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#endif
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switch (len) {
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case 1:
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out_8((u8 *) cfg_addr, val);
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break;
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case 2:
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out_le16((u16 *) cfg_addr, val);
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break;
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default:
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out_le32((u32 *) cfg_addr, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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void tsi108_clear_pci_error(u32 pci_cfg_base)
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{
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u32 err_stat, err_addr, pci_stat;
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/*
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* Quietly clear PB and PCI error flags set as result
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* of PCI/X configuration read requests.
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*/
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/* Read PB Error Log Registers */
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err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
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err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
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if (err_stat & TSI108_PB_ERRCS_ES) {
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/* Clear error flag */
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tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
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TSI108_PB_ERRCS_ES);
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/* Clear read error reported in PB_ISR */
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tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
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TSI108_PB_ISR_PBS_RD_ERR);
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/* Clear PCI/X bus cfg errors if applicable */
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if ((err_addr & 0xFF000000) == pci_cfg_base) {
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pci_stat =
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tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
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pci_stat);
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}
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}
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return;
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}
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#define __tsi108_read_pci_config(x, addr, op) \
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__asm__ __volatile__( \
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" "op" %0,0,%1\n" \
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"1: eieio\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: li %0,-1\n" \
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" b 2b\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 1b,3b\n" \
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".text" \
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: "=r"(x) : "r"(addr))
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int
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tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 * val)
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{
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volatile unsigned char *cfg_addr;
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struct pci_controller *hose = pci_bus_to_host(bus);
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u32 temp;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
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devfn,
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offset) | (offset &
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0x03));
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switch (len) {
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case 1:
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__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
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break;
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case 2:
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__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
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break;
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default:
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__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
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break;
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}
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*val = temp;
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#ifdef DEBUG
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if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
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printk("PCI CFG read : ");
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printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
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printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
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printk("data = 0x%x\n", *val);
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}
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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void tsi108_clear_pci_cfg_error(void)
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{
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tsi108_clear_pci_error(tsi108_pci_cfg_phys);
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}
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static struct pci_ops tsi108_direct_pci_ops = {
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.read = tsi108_direct_read_config,
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.write = tsi108_direct_write_config,
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};
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int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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int has_address = 0;
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/* PCI Config mapping */
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tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
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tsi108_pci_cfg_phys = cfg_phys;
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DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
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tsi108_pci_cfg_base);
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/* Fetch host bridge registers address */
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has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
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/* Get bus range if any */
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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}
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hose = pcibios_alloc_controller(dev);
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if (!hose) {
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printk("PCI Host bridge init failed\n");
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return -ENOMEM;
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}
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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(hose)->ops = &tsi108_direct_pci_ops;
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printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
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"Firmware bus number: %d->%d\n",
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rsrc.start, hose->first_busno, hose->last_busno);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev, primary);
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return 0;
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}
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/*
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* Low level utility functions
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*/
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static void tsi108_pci_int_mask(u_int irq)
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{
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u_int irp_cfg;
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int int_line = (irq - IRQ_PCI_INTAD_BASE);
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irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
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mb();
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irp_cfg |= (1 << int_line); /* INTx_DIR = output */
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irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
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mb();
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irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
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}
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static void tsi108_pci_int_unmask(u_int irq)
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{
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u_int irp_cfg;
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int int_line = (irq - IRQ_PCI_INTAD_BASE);
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irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
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mb();
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irp_cfg &= ~(1 << int_line);
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irp_cfg |= (3 << (8 + (int_line * 2)));
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
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mb();
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}
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static void init_pci_source(void)
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{
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
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0x0000ff00);
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
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TSI108_PCI_IRP_ENABLE_P_INT);
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mb();
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}
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static inline unsigned int get_pci_source(void)
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{
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u_int temp = 0;
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int irq = -1;
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int i;
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u_int pci_irp_stat;
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static int mask = 0;
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/* Read PCI/X block interrupt status register */
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pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
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mb();
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if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
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/* Process Interrupt from PCI bus INTA# - INTD# lines */
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temp =
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tsi108_read_reg(TSI108_PCI_OFFSET +
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TSI108_PCI_IRP_INTAD) & 0xf;
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mb();
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for (i = 0; i < 4; i++, mask++) {
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if (temp & (1 << mask % 4)) {
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irq = IRQ_PCI_INTA + mask % 4;
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mask++;
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break;
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}
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}
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/* Disable interrupts from PCI block */
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temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
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temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
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mb();
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(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
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mb();
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}
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#ifdef DEBUG
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else {
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printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
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pci_irp_stat =
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tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
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temp =
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tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
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mb();
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printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
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temp =
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tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
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mb();
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printk("cfg_ctl=0x%08x ", temp);
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temp =
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tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
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mb();
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printk("irp_enable=0x%08x\n", temp);
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}
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#endif /* end of DEBUG */
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return irq;
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}
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/*
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* Linux descriptor level callbacks
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*/
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static void tsi108_pci_irq_unmask(struct irq_data *d)
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{
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tsi108_pci_int_unmask(d->irq);
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/* Enable interrupts from PCI block */
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
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tsi108_read_reg(TSI108_PCI_OFFSET +
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TSI108_PCI_IRP_ENABLE) |
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TSI108_PCI_IRP_ENABLE_P_INT);
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mb();
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}
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static void tsi108_pci_irq_mask(struct irq_data *d)
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{
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tsi108_pci_int_mask(d->irq);
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}
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static void tsi108_pci_irq_ack(struct irq_data *d)
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{
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tsi108_pci_int_mask(d->irq);
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}
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/*
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* Interrupt controller descriptor for cascaded PCI interrupt controller.
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*/
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static struct irq_chip tsi108_pci_irq = {
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.name = "tsi108_PCI_int",
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.irq_mask = tsi108_pci_irq_mask,
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.irq_ack = tsi108_pci_irq_ack,
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.irq_unmask = tsi108_pci_irq_unmask,
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};
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static int pci_irq_host_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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*out_hwirq = intspec[0];
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*out_flags = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static int pci_irq_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{ unsigned int irq;
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DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
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if ((virq >= 1) && (virq <= 4)){
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irq = virq + IRQ_PCI_INTAD_BASE - 1;
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irq_set_status_flags(irq, IRQ_LEVEL);
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irq_set_chip(irq, &tsi108_pci_irq);
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}
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return 0;
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}
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static struct irq_domain_ops pci_irq_domain_ops = {
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.map = pci_irq_host_map,
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.xlate = pci_irq_host_xlate,
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};
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/*
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* Exported functions
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*/
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/*
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* The Tsi108 PCI interrupts initialization routine.
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*
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* The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
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* to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
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* PCI block has to be treated as a cascaded interrupt controller connected
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* to the MPIC.
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*/
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void __init tsi108_pci_int_init(struct device_node *node)
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{
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DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
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pci_irq_host = irq_domain_add_legacy(node, &pci_irq_domain_ops, NULL);
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if (pci_irq_host == NULL) {
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printk(KERN_ERR "pci_irq_host: failed to allocate irq domain!\n");
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return;
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}
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init_pci_source();
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}
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void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int cascade_irq = get_pci_source();
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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