forked from Minki/linux
a73f3382da
MDP5 hardware has some limitation and requires to avoid flushing registers more than once between two Vblanks. This change removes all FLUSH operations (except for HW cursor) beside the one coming from a CRTC's ->atomic_flush(). This avoid this type of behavior (eg: CRTC + 1 plane overlay): [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_ctl_commit] flush (20040) CTL + LM0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank and replaces it by: [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank Only *one* FLUSH is called between Vblanks interrupts. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com> |
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| .. | ||
| adreno | ||
| dsi | ||
| edp | ||
| hdmi | ||
| mdp | ||
| Kconfig | ||
| Makefile | ||
| msm_atomic.c | ||
| msm_drv.c | ||
| msm_drv.h | ||
| msm_fb.c | ||
| msm_fbdev.c | ||
| msm_gem_prime.c | ||
| msm_gem_submit.c | ||
| msm_gem.c | ||
| msm_gem.h | ||
| msm_gpu.c | ||
| msm_gpu.h | ||
| msm_iommu.c | ||
| msm_kms.h | ||
| msm_mmu.h | ||
| msm_perf.c | ||
| msm_rd.c | ||
| msm_ringbuffer.c | ||
| msm_ringbuffer.h | ||
| NOTES | ||