forked from Minki/linux
a702c8abb2
sdhci-pltfm driver for PXAV3 SoCs, such as MMP2. Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Philip Rakity <prakity@marvell.com> Acked-by: Philip Rakity <prakity@marvell.com> Acked-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>
290 lines
7.2 KiB
C
290 lines
7.2 KiB
C
/*
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* Copyright (C) 2010 Marvell International Ltd.
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* Zhangfei Gao <zhangfei.gao@marvell.com>
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* Kevin Wang <dwang4@marvell.com>
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* Mingwei Wang <mwwang@marvell.com>
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* Philip Rakity <prakity@marvell.com>
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* Mark Brown <markb@marvell.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <plat/sdhci.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
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#define SDCLK_SEL 0x100
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#define SDCLK_DELAY_SHIFT 9
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#define SDCLK_DELAY_MASK 0x1f
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#define SD_CFG_FIFO_PARAM 0x100
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#define SDCFG_GEN_PAD_CLK_ON (1<<6)
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#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
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#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
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#define SD_SPI_MODE 0x108
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#define SD_CE_ATA_1 0x10C
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#define SD_CE_ATA_2 0x10E
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#define SDCE_MISC_INT (1<<2)
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#define SDCE_MISC_INT_EN (1<<1)
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static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
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{
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struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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if (mask == SDHCI_RESET_ALL) {
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/*
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* tune timing of read data/command when crc error happen
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* no performance impact
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*/
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if (pdata && 0 != pdata->clk_delay_cycles) {
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u16 tmp;
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tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
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<< SDCLK_DELAY_SHIFT;
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tmp |= SDCLK_SEL;
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writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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}
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}
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}
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#define MAX_WAIT_COUNT 5
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static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_pxa *pxa = pltfm_host->priv;
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u16 tmp;
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int count;
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if (pxa->power_mode == MMC_POWER_UP
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&& power_mode == MMC_POWER_ON) {
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dev_dbg(mmc_dev(host->mmc),
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"%s: slot->power_mode = %d,"
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"ios->power_mode = %d\n",
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__func__,
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pxa->power_mode,
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power_mode);
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/* set we want notice of when 74 clocks are sent */
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tmp = readw(host->ioaddr + SD_CE_ATA_2);
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tmp |= SDCE_MISC_INT_EN;
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writew(tmp, host->ioaddr + SD_CE_ATA_2);
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/* start sending the 74 clocks */
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tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
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tmp |= SDCFG_GEN_PAD_CLK_ON;
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writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
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/* slowest speed is about 100KHz or 10usec per clock */
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udelay(740);
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count = 0;
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while (count++ < MAX_WAIT_COUNT) {
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if ((readw(host->ioaddr + SD_CE_ATA_2)
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& SDCE_MISC_INT) == 0)
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break;
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udelay(10);
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}
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if (count == MAX_WAIT_COUNT)
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dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
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/* clear the interrupt bit if posted */
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tmp = readw(host->ioaddr + SD_CE_ATA_2);
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tmp |= SDCE_MISC_INT;
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writew(tmp, host->ioaddr + SD_CE_ATA_2);
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}
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pxa->power_mode = power_mode;
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}
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static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
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{
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u16 ctrl_2;
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/*
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* Set V18_EN -- UHS modes do not work without this.
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* does not change signaling voltage
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*/
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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switch (uhs) {
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case MMC_TIMING_UHS_SDR12:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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break;
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case MMC_TIMING_UHS_SDR25:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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break;
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case MMC_TIMING_UHS_SDR50:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
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break;
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case MMC_TIMING_UHS_SDR104:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
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break;
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case MMC_TIMING_UHS_DDR50:
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
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break;
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}
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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dev_dbg(mmc_dev(host->mmc),
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"%s uhs = %d, ctrl_2 = %04X\n",
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__func__, uhs, ctrl_2);
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return 0;
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}
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static struct sdhci_ops pxav3_sdhci_ops = {
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.platform_reset_exit = pxav3_set_private_registers,
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.set_uhs_signaling = pxav3_set_uhs_signaling,
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.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
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};
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static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
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{
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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struct device *dev = &pdev->dev;
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struct sdhci_host *host = NULL;
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struct sdhci_pxa *pxa = NULL;
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int ret;
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struct clk *clk;
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pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
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if (!pxa)
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return -ENOMEM;
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host = sdhci_pltfm_init(pdev, NULL);
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if (IS_ERR(host)) {
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kfree(pxa);
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return PTR_ERR(host);
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}
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pltfm_host = sdhci_priv(host);
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pltfm_host->priv = pxa;
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clk = clk_get(dev, "PXA-SDHCLK");
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get io clock\n");
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ret = PTR_ERR(clk);
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goto err_clk_get;
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}
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pltfm_host->clk = clk;
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clk_enable(clk);
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host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
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| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
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/* enable 1/8V DDR capable */
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host->mmc->caps |= MMC_CAP_1_8V_DDR;
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if (pdata) {
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if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
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/* on-chip device */
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host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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host->mmc->caps |= MMC_CAP_NONREMOVABLE;
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}
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/* If slot design supports 8 bit data, indicate this to MMC. */
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if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
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host->mmc->caps |= MMC_CAP_8_BIT_DATA;
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if (pdata->quirks)
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host->quirks |= pdata->quirks;
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if (pdata->host_caps)
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host->mmc->caps |= pdata->host_caps;
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if (pdata->pm_caps)
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host->mmc->pm_caps |= pdata->pm_caps;
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}
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host->ops = &pxav3_sdhci_ops;
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ret = sdhci_add_host(host);
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if (ret) {
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dev_err(&pdev->dev, "failed to add host\n");
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goto err_add_host;
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}
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platform_set_drvdata(pdev, host);
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return 0;
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err_add_host:
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clk_disable(clk);
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clk_put(clk);
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err_clk_get:
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sdhci_pltfm_free(pdev);
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kfree(pxa);
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return ret;
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}
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static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_pxa *pxa = pltfm_host->priv;
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sdhci_remove_host(host, 1);
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clk_disable(pltfm_host->clk);
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clk_put(pltfm_host->clk);
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sdhci_pltfm_free(pdev);
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kfree(pxa);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver sdhci_pxav3_driver = {
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.driver = {
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.name = "sdhci-pxav3",
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.owner = THIS_MODULE,
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},
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.probe = sdhci_pxav3_probe,
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.remove = __devexit_p(sdhci_pxav3_remove),
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#ifdef CONFIG_PM
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.suspend = sdhci_pltfm_suspend,
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.resume = sdhci_pltfm_resume,
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#endif
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};
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static int __init sdhci_pxav3_init(void)
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{
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return platform_driver_register(&sdhci_pxav3_driver);
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}
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static void __exit sdhci_pxav3_exit(void)
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{
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platform_driver_unregister(&sdhci_pxav3_driver);
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}
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module_init(sdhci_pxav3_init);
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module_exit(sdhci_pxav3_exit);
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MODULE_DESCRIPTION("SDHCI driver for pxav3");
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MODULE_AUTHOR("Marvell International Ltd.");
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MODULE_LICENSE("GPL v2");
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