forked from Minki/linux
4793 lines
163 KiB
C
4793 lines
163 KiB
C
#ifndef A5XX_XML
|
|
#define A5XX_XML
|
|
|
|
/* Autogenerated file, DO NOT EDIT manually!
|
|
|
|
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
|
http://github.com/freedreno/envytools/
|
|
git clone https://github.com/freedreno/envytools.git
|
|
|
|
The rules-ng-ng source files this header was generated from are:
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
|
|
|
Copyright (C) 2013-2017 by the following authors:
|
|
- Rob Clark <robdclark@gmail.com> (robclark)
|
|
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
|
|
|
Permission is hereby granted, free of charge, to any person obtaining
|
|
a copy of this software and associated documentation files (the
|
|
"Software"), to deal in the Software without restriction, including
|
|
without limitation the rights to use, copy, modify, merge, publish,
|
|
distribute, sublicense, and/or sell copies of the Software, and to
|
|
permit persons to whom the Software is furnished to do so, subject to
|
|
the following conditions:
|
|
|
|
The above copyright notice and this permission notice (including the
|
|
next paragraph) shall be included in all copies or substantial
|
|
portions of the Software.
|
|
|
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
|
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
|
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
|
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
|
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
|
|
enum a5xx_color_fmt {
|
|
RB5_A8_UNORM = 2,
|
|
RB5_R8_UNORM = 3,
|
|
RB5_R8_SNORM = 4,
|
|
RB5_R8_UINT = 5,
|
|
RB5_R8_SINT = 6,
|
|
RB5_R4G4B4A4_UNORM = 8,
|
|
RB5_R5G5B5A1_UNORM = 10,
|
|
RB5_R5G6B5_UNORM = 14,
|
|
RB5_R8G8_UNORM = 15,
|
|
RB5_R8G8_SNORM = 16,
|
|
RB5_R8G8_UINT = 17,
|
|
RB5_R8G8_SINT = 18,
|
|
RB5_R16_UNORM = 21,
|
|
RB5_R16_SNORM = 22,
|
|
RB5_R16_FLOAT = 23,
|
|
RB5_R16_UINT = 24,
|
|
RB5_R16_SINT = 25,
|
|
RB5_R8G8B8A8_UNORM = 48,
|
|
RB5_R8G8B8_UNORM = 49,
|
|
RB5_R8G8B8A8_SNORM = 50,
|
|
RB5_R8G8B8A8_UINT = 51,
|
|
RB5_R8G8B8A8_SINT = 52,
|
|
RB5_R10G10B10A2_UNORM = 55,
|
|
RB5_R10G10B10A2_UINT = 58,
|
|
RB5_R11G11B10_FLOAT = 66,
|
|
RB5_R16G16_UNORM = 67,
|
|
RB5_R16G16_SNORM = 68,
|
|
RB5_R16G16_FLOAT = 69,
|
|
RB5_R16G16_UINT = 70,
|
|
RB5_R16G16_SINT = 71,
|
|
RB5_R32_FLOAT = 74,
|
|
RB5_R32_UINT = 75,
|
|
RB5_R32_SINT = 76,
|
|
RB5_R16G16B16A16_UNORM = 96,
|
|
RB5_R16G16B16A16_SNORM = 97,
|
|
RB5_R16G16B16A16_FLOAT = 98,
|
|
RB5_R16G16B16A16_UINT = 99,
|
|
RB5_R16G16B16A16_SINT = 100,
|
|
RB5_R32G32_FLOAT = 103,
|
|
RB5_R32G32_UINT = 104,
|
|
RB5_R32G32_SINT = 105,
|
|
RB5_R32G32B32A32_FLOAT = 130,
|
|
RB5_R32G32B32A32_UINT = 131,
|
|
RB5_R32G32B32A32_SINT = 132,
|
|
};
|
|
|
|
enum a5xx_tile_mode {
|
|
TILE5_LINEAR = 0,
|
|
TILE5_2 = 2,
|
|
TILE5_3 = 3,
|
|
};
|
|
|
|
enum a5xx_vtx_fmt {
|
|
VFMT5_8_UNORM = 3,
|
|
VFMT5_8_SNORM = 4,
|
|
VFMT5_8_UINT = 5,
|
|
VFMT5_8_SINT = 6,
|
|
VFMT5_8_8_UNORM = 15,
|
|
VFMT5_8_8_SNORM = 16,
|
|
VFMT5_8_8_UINT = 17,
|
|
VFMT5_8_8_SINT = 18,
|
|
VFMT5_16_UNORM = 21,
|
|
VFMT5_16_SNORM = 22,
|
|
VFMT5_16_FLOAT = 23,
|
|
VFMT5_16_UINT = 24,
|
|
VFMT5_16_SINT = 25,
|
|
VFMT5_8_8_8_UNORM = 33,
|
|
VFMT5_8_8_8_SNORM = 34,
|
|
VFMT5_8_8_8_UINT = 35,
|
|
VFMT5_8_8_8_SINT = 36,
|
|
VFMT5_8_8_8_8_UNORM = 48,
|
|
VFMT5_8_8_8_8_SNORM = 50,
|
|
VFMT5_8_8_8_8_UINT = 51,
|
|
VFMT5_8_8_8_8_SINT = 52,
|
|
VFMT5_16_16_UNORM = 67,
|
|
VFMT5_16_16_SNORM = 68,
|
|
VFMT5_16_16_FLOAT = 69,
|
|
VFMT5_16_16_UINT = 70,
|
|
VFMT5_16_16_SINT = 71,
|
|
VFMT5_32_UNORM = 72,
|
|
VFMT5_32_SNORM = 73,
|
|
VFMT5_32_FLOAT = 74,
|
|
VFMT5_32_UINT = 75,
|
|
VFMT5_32_SINT = 76,
|
|
VFMT5_32_FIXED = 77,
|
|
VFMT5_16_16_16_UNORM = 88,
|
|
VFMT5_16_16_16_SNORM = 89,
|
|
VFMT5_16_16_16_FLOAT = 90,
|
|
VFMT5_16_16_16_UINT = 91,
|
|
VFMT5_16_16_16_SINT = 92,
|
|
VFMT5_16_16_16_16_UNORM = 96,
|
|
VFMT5_16_16_16_16_SNORM = 97,
|
|
VFMT5_16_16_16_16_FLOAT = 98,
|
|
VFMT5_16_16_16_16_UINT = 99,
|
|
VFMT5_16_16_16_16_SINT = 100,
|
|
VFMT5_32_32_UNORM = 101,
|
|
VFMT5_32_32_SNORM = 102,
|
|
VFMT5_32_32_FLOAT = 103,
|
|
VFMT5_32_32_UINT = 104,
|
|
VFMT5_32_32_SINT = 105,
|
|
VFMT5_32_32_FIXED = 106,
|
|
VFMT5_32_32_32_UNORM = 112,
|
|
VFMT5_32_32_32_SNORM = 113,
|
|
VFMT5_32_32_32_UINT = 114,
|
|
VFMT5_32_32_32_SINT = 115,
|
|
VFMT5_32_32_32_FLOAT = 116,
|
|
VFMT5_32_32_32_FIXED = 117,
|
|
VFMT5_32_32_32_32_UNORM = 128,
|
|
VFMT5_32_32_32_32_SNORM = 129,
|
|
VFMT5_32_32_32_32_FLOAT = 130,
|
|
VFMT5_32_32_32_32_UINT = 131,
|
|
VFMT5_32_32_32_32_SINT = 132,
|
|
VFMT5_32_32_32_32_FIXED = 133,
|
|
};
|
|
|
|
enum a5xx_tex_fmt {
|
|
TFMT5_A8_UNORM = 2,
|
|
TFMT5_8_UNORM = 3,
|
|
TFMT5_8_SNORM = 4,
|
|
TFMT5_8_UINT = 5,
|
|
TFMT5_8_SINT = 6,
|
|
TFMT5_4_4_4_4_UNORM = 8,
|
|
TFMT5_5_5_5_1_UNORM = 10,
|
|
TFMT5_5_6_5_UNORM = 14,
|
|
TFMT5_8_8_UNORM = 15,
|
|
TFMT5_8_8_SNORM = 16,
|
|
TFMT5_8_8_UINT = 17,
|
|
TFMT5_8_8_SINT = 18,
|
|
TFMT5_L8_A8_UNORM = 19,
|
|
TFMT5_16_UNORM = 21,
|
|
TFMT5_16_SNORM = 22,
|
|
TFMT5_16_FLOAT = 23,
|
|
TFMT5_16_UINT = 24,
|
|
TFMT5_16_SINT = 25,
|
|
TFMT5_8_8_8_8_UNORM = 48,
|
|
TFMT5_8_8_8_UNORM = 49,
|
|
TFMT5_8_8_8_8_SNORM = 50,
|
|
TFMT5_8_8_8_8_UINT = 51,
|
|
TFMT5_8_8_8_8_SINT = 52,
|
|
TFMT5_9_9_9_E5_FLOAT = 53,
|
|
TFMT5_10_10_10_2_UNORM = 54,
|
|
TFMT5_10_10_10_2_UINT = 58,
|
|
TFMT5_11_11_10_FLOAT = 66,
|
|
TFMT5_16_16_UNORM = 67,
|
|
TFMT5_16_16_SNORM = 68,
|
|
TFMT5_16_16_FLOAT = 69,
|
|
TFMT5_16_16_UINT = 70,
|
|
TFMT5_16_16_SINT = 71,
|
|
TFMT5_32_FLOAT = 74,
|
|
TFMT5_32_UINT = 75,
|
|
TFMT5_32_SINT = 76,
|
|
TFMT5_16_16_16_16_UNORM = 96,
|
|
TFMT5_16_16_16_16_SNORM = 97,
|
|
TFMT5_16_16_16_16_FLOAT = 98,
|
|
TFMT5_16_16_16_16_UINT = 99,
|
|
TFMT5_16_16_16_16_SINT = 100,
|
|
TFMT5_32_32_FLOAT = 103,
|
|
TFMT5_32_32_UINT = 104,
|
|
TFMT5_32_32_SINT = 105,
|
|
TFMT5_32_32_32_32_FLOAT = 130,
|
|
TFMT5_32_32_32_32_UINT = 131,
|
|
TFMT5_32_32_32_32_SINT = 132,
|
|
TFMT5_X8Z24_UNORM = 160,
|
|
TFMT5_RGTC1_UNORM = 183,
|
|
TFMT5_RGTC1_SNORM = 184,
|
|
TFMT5_RGTC2_UNORM = 187,
|
|
TFMT5_RGTC2_SNORM = 188,
|
|
};
|
|
|
|
enum a5xx_tex_fetchsize {
|
|
TFETCH5_1_BYTE = 0,
|
|
TFETCH5_2_BYTE = 1,
|
|
TFETCH5_4_BYTE = 2,
|
|
TFETCH5_8_BYTE = 3,
|
|
TFETCH5_16_BYTE = 4,
|
|
};
|
|
|
|
enum a5xx_depth_format {
|
|
DEPTH5_NONE = 0,
|
|
DEPTH5_16 = 1,
|
|
DEPTH5_24_8 = 2,
|
|
DEPTH5_32 = 4,
|
|
};
|
|
|
|
enum a5xx_blit_buf {
|
|
BLIT_MRT0 = 0,
|
|
BLIT_MRT1 = 1,
|
|
BLIT_MRT2 = 2,
|
|
BLIT_MRT3 = 3,
|
|
BLIT_MRT4 = 4,
|
|
BLIT_MRT5 = 5,
|
|
BLIT_MRT6 = 6,
|
|
BLIT_MRT7 = 7,
|
|
BLIT_ZS = 8,
|
|
BLIT_Z32 = 9,
|
|
};
|
|
|
|
enum a5xx_cp_perfcounter_select {
|
|
PERF_CP_ALWAYS_COUNT = 0,
|
|
PERF_CP_BUSY_GFX_CORE_IDLE = 1,
|
|
PERF_CP_BUSY_CYCLES = 2,
|
|
PERF_CP_PFP_IDLE = 3,
|
|
PERF_CP_PFP_BUSY_WORKING = 4,
|
|
PERF_CP_PFP_STALL_CYCLES_ANY = 5,
|
|
PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
|
|
PERF_CP_PFP_ICACHE_MISS = 7,
|
|
PERF_CP_PFP_ICACHE_HIT = 8,
|
|
PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
|
|
PERF_CP_ME_BUSY_WORKING = 10,
|
|
PERF_CP_ME_IDLE = 11,
|
|
PERF_CP_ME_STARVE_CYCLES_ANY = 12,
|
|
PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
|
|
PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
|
|
PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
|
|
PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
|
|
PERF_CP_ME_STALL_CYCLES_ANY = 17,
|
|
PERF_CP_ME_ICACHE_MISS = 18,
|
|
PERF_CP_ME_ICACHE_HIT = 19,
|
|
PERF_CP_NUM_PREEMPTIONS = 20,
|
|
PERF_CP_PREEMPTION_REACTION_DELAY = 21,
|
|
PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
|
|
PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
|
|
PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
|
|
PERF_CP_PREDICATED_DRAWS_KILLED = 25,
|
|
PERF_CP_MODE_SWITCH = 26,
|
|
PERF_CP_ZPASS_DONE = 27,
|
|
PERF_CP_CONTEXT_DONE = 28,
|
|
PERF_CP_CACHE_FLUSH = 29,
|
|
PERF_CP_LONG_PREEMPTIONS = 30,
|
|
};
|
|
|
|
enum a5xx_rbbm_perfcounter_select {
|
|
PERF_RBBM_ALWAYS_COUNT = 0,
|
|
PERF_RBBM_ALWAYS_ON = 1,
|
|
PERF_RBBM_TSE_BUSY = 2,
|
|
PERF_RBBM_RAS_BUSY = 3,
|
|
PERF_RBBM_PC_DCALL_BUSY = 4,
|
|
PERF_RBBM_PC_VSD_BUSY = 5,
|
|
PERF_RBBM_STATUS_MASKED = 6,
|
|
PERF_RBBM_COM_BUSY = 7,
|
|
PERF_RBBM_DCOM_BUSY = 8,
|
|
PERF_RBBM_VBIF_BUSY = 9,
|
|
PERF_RBBM_VSC_BUSY = 10,
|
|
PERF_RBBM_TESS_BUSY = 11,
|
|
PERF_RBBM_UCHE_BUSY = 12,
|
|
PERF_RBBM_HLSQ_BUSY = 13,
|
|
};
|
|
|
|
enum a5xx_pc_perfcounter_select {
|
|
PERF_PC_BUSY_CYCLES = 0,
|
|
PERF_PC_WORKING_CYCLES = 1,
|
|
PERF_PC_STALL_CYCLES_VFD = 2,
|
|
PERF_PC_STALL_CYCLES_TSE = 3,
|
|
PERF_PC_STALL_CYCLES_VPC = 4,
|
|
PERF_PC_STALL_CYCLES_UCHE = 5,
|
|
PERF_PC_STALL_CYCLES_TESS = 6,
|
|
PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
|
|
PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
|
|
PERF_PC_PASS1_TF_STALL_CYCLES = 9,
|
|
PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
|
|
PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
|
|
PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
|
|
PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
|
|
PERF_PC_STARVE_CYCLES_DI = 14,
|
|
PERF_PC_VIS_STREAMS_LOADED = 15,
|
|
PERF_PC_INSTANCES = 16,
|
|
PERF_PC_VPC_PRIMITIVES = 17,
|
|
PERF_PC_DEAD_PRIM = 18,
|
|
PERF_PC_LIVE_PRIM = 19,
|
|
PERF_PC_VERTEX_HITS = 20,
|
|
PERF_PC_IA_VERTICES = 21,
|
|
PERF_PC_IA_PRIMITIVES = 22,
|
|
PERF_PC_GS_PRIMITIVES = 23,
|
|
PERF_PC_HS_INVOCATIONS = 24,
|
|
PERF_PC_DS_INVOCATIONS = 25,
|
|
PERF_PC_VS_INVOCATIONS = 26,
|
|
PERF_PC_GS_INVOCATIONS = 27,
|
|
PERF_PC_DS_PRIMITIVES = 28,
|
|
PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
|
|
PERF_PC_3D_DRAWCALLS = 30,
|
|
PERF_PC_2D_DRAWCALLS = 31,
|
|
PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
|
|
PERF_TESS_BUSY_CYCLES = 33,
|
|
PERF_TESS_WORKING_CYCLES = 34,
|
|
PERF_TESS_STALL_CYCLES_PC = 35,
|
|
PERF_TESS_STARVE_CYCLES_PC = 36,
|
|
};
|
|
|
|
enum a5xx_vfd_perfcounter_select {
|
|
PERF_VFD_BUSY_CYCLES = 0,
|
|
PERF_VFD_STALL_CYCLES_UCHE = 1,
|
|
PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
|
|
PERF_VFD_STALL_CYCLES_MISS_VB = 3,
|
|
PERF_VFD_STALL_CYCLES_MISS_Q = 4,
|
|
PERF_VFD_STALL_CYCLES_SP_INFO = 5,
|
|
PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
|
|
PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
|
|
PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
|
|
PERF_VFD_DECODER_PACKER_STALL = 9,
|
|
PERF_VFD_STARVE_CYCLES_UCHE = 10,
|
|
PERF_VFD_RBUFFER_FULL = 11,
|
|
PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
|
|
PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
|
|
PERF_VFD_NUM_ATTRIBUTES = 14,
|
|
PERF_VFD_INSTRUCTIONS = 15,
|
|
PERF_VFD_UPPER_SHADER_FIBERS = 16,
|
|
PERF_VFD_LOWER_SHADER_FIBERS = 17,
|
|
PERF_VFD_MODE_0_FIBERS = 18,
|
|
PERF_VFD_MODE_1_FIBERS = 19,
|
|
PERF_VFD_MODE_2_FIBERS = 20,
|
|
PERF_VFD_MODE_3_FIBERS = 21,
|
|
PERF_VFD_MODE_4_FIBERS = 22,
|
|
PERF_VFD_TOTAL_VERTICES = 23,
|
|
PERF_VFD_NUM_ATTR_MISS = 24,
|
|
PERF_VFD_1_BURST_REQ = 25,
|
|
PERF_VFDP_STALL_CYCLES_VFD = 26,
|
|
PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
|
|
PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
|
|
PERF_VFDP_STARVE_CYCLES_PC = 29,
|
|
PERF_VFDP_VS_STAGE_32_WAVES = 30,
|
|
};
|
|
|
|
enum a5xx_hlsq_perfcounter_select {
|
|
PERF_HLSQ_BUSY_CYCLES = 0,
|
|
PERF_HLSQ_STALL_CYCLES_UCHE = 1,
|
|
PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
|
|
PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
|
|
PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
|
|
PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
|
|
PERF_HLSQ_FS_STAGE_32_WAVES = 6,
|
|
PERF_HLSQ_FS_STAGE_64_WAVES = 7,
|
|
PERF_HLSQ_QUADS = 8,
|
|
PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
|
|
PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
|
|
PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
|
|
PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
|
|
PERF_HLSQ_CS_INVOCATIONS = 13,
|
|
PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
|
|
};
|
|
|
|
enum a5xx_vpc_perfcounter_select {
|
|
PERF_VPC_BUSY_CYCLES = 0,
|
|
PERF_VPC_WORKING_CYCLES = 1,
|
|
PERF_VPC_STALL_CYCLES_UCHE = 2,
|
|
PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
|
|
PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
|
|
PERF_VPC_STALL_CYCLES_PC = 5,
|
|
PERF_VPC_STALL_CYCLES_SP_LM = 6,
|
|
PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
|
|
PERF_VPC_STARVE_CYCLES_SP = 8,
|
|
PERF_VPC_STARVE_CYCLES_LRZ = 9,
|
|
PERF_VPC_PC_PRIMITIVES = 10,
|
|
PERF_VPC_SP_COMPONENTS = 11,
|
|
PERF_VPC_SP_LM_PRIMITIVES = 12,
|
|
PERF_VPC_SP_LM_COMPONENTS = 13,
|
|
PERF_VPC_SP_LM_DWORDS = 14,
|
|
PERF_VPC_STREAMOUT_COMPONENTS = 15,
|
|
PERF_VPC_GRANT_PHASES = 16,
|
|
};
|
|
|
|
enum a5xx_tse_perfcounter_select {
|
|
PERF_TSE_BUSY_CYCLES = 0,
|
|
PERF_TSE_CLIPPING_CYCLES = 1,
|
|
PERF_TSE_STALL_CYCLES_RAS = 2,
|
|
PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
|
|
PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
|
|
PERF_TSE_STARVE_CYCLES_PC = 5,
|
|
PERF_TSE_INPUT_PRIM = 6,
|
|
PERF_TSE_INPUT_NULL_PRIM = 7,
|
|
PERF_TSE_TRIVAL_REJ_PRIM = 8,
|
|
PERF_TSE_CLIPPED_PRIM = 9,
|
|
PERF_TSE_ZERO_AREA_PRIM = 10,
|
|
PERF_TSE_FACENESS_CULLED_PRIM = 11,
|
|
PERF_TSE_ZERO_PIXEL_PRIM = 12,
|
|
PERF_TSE_OUTPUT_NULL_PRIM = 13,
|
|
PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
|
|
PERF_TSE_CINVOCATION = 15,
|
|
PERF_TSE_CPRIMITIVES = 16,
|
|
PERF_TSE_2D_INPUT_PRIM = 17,
|
|
PERF_TSE_2D_ALIVE_CLCLES = 18,
|
|
};
|
|
|
|
enum a5xx_ras_perfcounter_select {
|
|
PERF_RAS_BUSY_CYCLES = 0,
|
|
PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
|
|
PERF_RAS_STALL_CYCLES_LRZ = 2,
|
|
PERF_RAS_STARVE_CYCLES_TSE = 3,
|
|
PERF_RAS_SUPER_TILES = 4,
|
|
PERF_RAS_8X4_TILES = 5,
|
|
PERF_RAS_MASKGEN_ACTIVE = 6,
|
|
PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
|
|
PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
|
|
PERF_RAS_PRIM_KILLED_INVISILBE = 9,
|
|
};
|
|
|
|
enum a5xx_lrz_perfcounter_select {
|
|
PERF_LRZ_BUSY_CYCLES = 0,
|
|
PERF_LRZ_STARVE_CYCLES_RAS = 1,
|
|
PERF_LRZ_STALL_CYCLES_RB = 2,
|
|
PERF_LRZ_STALL_CYCLES_VSC = 3,
|
|
PERF_LRZ_STALL_CYCLES_VPC = 4,
|
|
PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
|
|
PERF_LRZ_STALL_CYCLES_UCHE = 6,
|
|
PERF_LRZ_LRZ_READ = 7,
|
|
PERF_LRZ_LRZ_WRITE = 8,
|
|
PERF_LRZ_READ_LATENCY = 9,
|
|
PERF_LRZ_MERGE_CACHE_UPDATING = 10,
|
|
PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
|
|
PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
|
|
PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
|
|
PERF_LRZ_FULL_8X8_TILES = 14,
|
|
PERF_LRZ_PARTIAL_8X8_TILES = 15,
|
|
PERF_LRZ_TILE_KILLED = 16,
|
|
PERF_LRZ_TOTAL_PIXEL = 17,
|
|
PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
|
|
};
|
|
|
|
enum a5xx_uche_perfcounter_select {
|
|
PERF_UCHE_BUSY_CYCLES = 0,
|
|
PERF_UCHE_STALL_CYCLES_VBIF = 1,
|
|
PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
|
|
PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
|
|
PERF_UCHE_VBIF_READ_BEATS_TP = 4,
|
|
PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
|
|
PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
|
|
PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
|
|
PERF_UCHE_VBIF_READ_BEATS_SP = 8,
|
|
PERF_UCHE_READ_REQUESTS_TP = 9,
|
|
PERF_UCHE_READ_REQUESTS_VFD = 10,
|
|
PERF_UCHE_READ_REQUESTS_HLSQ = 11,
|
|
PERF_UCHE_READ_REQUESTS_LRZ = 12,
|
|
PERF_UCHE_READ_REQUESTS_SP = 13,
|
|
PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
|
|
PERF_UCHE_WRITE_REQUESTS_SP = 15,
|
|
PERF_UCHE_WRITE_REQUESTS_VPC = 16,
|
|
PERF_UCHE_WRITE_REQUESTS_VSC = 17,
|
|
PERF_UCHE_EVICTS = 18,
|
|
PERF_UCHE_BANK_REQ0 = 19,
|
|
PERF_UCHE_BANK_REQ1 = 20,
|
|
PERF_UCHE_BANK_REQ2 = 21,
|
|
PERF_UCHE_BANK_REQ3 = 22,
|
|
PERF_UCHE_BANK_REQ4 = 23,
|
|
PERF_UCHE_BANK_REQ5 = 24,
|
|
PERF_UCHE_BANK_REQ6 = 25,
|
|
PERF_UCHE_BANK_REQ7 = 26,
|
|
PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
|
|
PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
|
|
PERF_UCHE_GMEM_READ_BEATS = 29,
|
|
PERF_UCHE_FLAG_COUNT = 30,
|
|
};
|
|
|
|
enum a5xx_tp_perfcounter_select {
|
|
PERF_TP_BUSY_CYCLES = 0,
|
|
PERF_TP_STALL_CYCLES_UCHE = 1,
|
|
PERF_TP_LATENCY_CYCLES = 2,
|
|
PERF_TP_LATENCY_TRANS = 3,
|
|
PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
|
|
PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
|
|
PERF_TP_L1_CACHELINE_REQUESTS = 6,
|
|
PERF_TP_L1_CACHELINE_MISSES = 7,
|
|
PERF_TP_SP_TP_TRANS = 8,
|
|
PERF_TP_TP_SP_TRANS = 9,
|
|
PERF_TP_OUTPUT_PIXELS = 10,
|
|
PERF_TP_FILTER_WORKLOAD_16BIT = 11,
|
|
PERF_TP_FILTER_WORKLOAD_32BIT = 12,
|
|
PERF_TP_QUADS_RECEIVED = 13,
|
|
PERF_TP_QUADS_OFFSET = 14,
|
|
PERF_TP_QUADS_SHADOW = 15,
|
|
PERF_TP_QUADS_ARRAY = 16,
|
|
PERF_TP_QUADS_GRADIENT = 17,
|
|
PERF_TP_QUADS_1D = 18,
|
|
PERF_TP_QUADS_2D = 19,
|
|
PERF_TP_QUADS_BUFFER = 20,
|
|
PERF_TP_QUADS_3D = 21,
|
|
PERF_TP_QUADS_CUBE = 22,
|
|
PERF_TP_STATE_CACHE_REQUESTS = 23,
|
|
PERF_TP_STATE_CACHE_MISSES = 24,
|
|
PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
|
|
PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
|
|
PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
|
|
PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
|
|
PERF_TP_OUTPUT_PIXELS_POINT = 29,
|
|
PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
|
|
PERF_TP_OUTPUT_PIXELS_MIP = 31,
|
|
PERF_TP_OUTPUT_PIXELS_ANISO = 32,
|
|
PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
|
|
PERF_TP_FLAG_CACHE_REQUESTS = 34,
|
|
PERF_TP_FLAG_CACHE_MISSES = 35,
|
|
PERF_TP_L1_5_L2_REQUESTS = 36,
|
|
PERF_TP_2D_OUTPUT_PIXELS = 37,
|
|
PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
|
|
PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
|
|
PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
|
|
PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
|
|
};
|
|
|
|
enum a5xx_sp_perfcounter_select {
|
|
PERF_SP_BUSY_CYCLES = 0,
|
|
PERF_SP_ALU_WORKING_CYCLES = 1,
|
|
PERF_SP_EFU_WORKING_CYCLES = 2,
|
|
PERF_SP_STALL_CYCLES_VPC = 3,
|
|
PERF_SP_STALL_CYCLES_TP = 4,
|
|
PERF_SP_STALL_CYCLES_UCHE = 5,
|
|
PERF_SP_STALL_CYCLES_RB = 6,
|
|
PERF_SP_SCHEDULER_NON_WORKING = 7,
|
|
PERF_SP_WAVE_CONTEXTS = 8,
|
|
PERF_SP_WAVE_CONTEXT_CYCLES = 9,
|
|
PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
|
|
PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
|
|
PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
|
|
PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
|
|
PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
|
|
PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
|
|
PERF_SP_WAVE_CTRL_CYCLES = 16,
|
|
PERF_SP_WAVE_LOAD_CYCLES = 17,
|
|
PERF_SP_WAVE_EMIT_CYCLES = 18,
|
|
PERF_SP_WAVE_NOP_CYCLES = 19,
|
|
PERF_SP_WAVE_WAIT_CYCLES = 20,
|
|
PERF_SP_WAVE_FETCH_CYCLES = 21,
|
|
PERF_SP_WAVE_IDLE_CYCLES = 22,
|
|
PERF_SP_WAVE_END_CYCLES = 23,
|
|
PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
|
|
PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
|
|
PERF_SP_WAVE_JOIN_CYCLES = 26,
|
|
PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
|
|
PERF_SP_LM_STORE_INSTRUCTIONS = 28,
|
|
PERF_SP_LM_ATOMICS = 29,
|
|
PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
|
|
PERF_SP_GM_STORE_INSTRUCTIONS = 31,
|
|
PERF_SP_GM_ATOMICS = 32,
|
|
PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
|
|
PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
|
|
PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
|
|
PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
|
|
PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
|
|
PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
|
|
PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
|
|
PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
|
|
PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
|
|
PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
|
|
PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
|
|
PERF_SP_VS_INSTRUCTIONS = 44,
|
|
PERF_SP_FS_INSTRUCTIONS = 45,
|
|
PERF_SP_ADDR_LOCK_COUNT = 46,
|
|
PERF_SP_UCHE_READ_TRANS = 47,
|
|
PERF_SP_UCHE_WRITE_TRANS = 48,
|
|
PERF_SP_EXPORT_VPC_TRANS = 49,
|
|
PERF_SP_EXPORT_RB_TRANS = 50,
|
|
PERF_SP_PIXELS_KILLED = 51,
|
|
PERF_SP_ICL1_REQUESTS = 52,
|
|
PERF_SP_ICL1_MISSES = 53,
|
|
PERF_SP_ICL0_REQUESTS = 54,
|
|
PERF_SP_ICL0_MISSES = 55,
|
|
PERF_SP_HS_INSTRUCTIONS = 56,
|
|
PERF_SP_DS_INSTRUCTIONS = 57,
|
|
PERF_SP_GS_INSTRUCTIONS = 58,
|
|
PERF_SP_CS_INSTRUCTIONS = 59,
|
|
PERF_SP_GPR_READ = 60,
|
|
PERF_SP_GPR_WRITE = 61,
|
|
PERF_SP_LM_CH0_REQUESTS = 62,
|
|
PERF_SP_LM_CH1_REQUESTS = 63,
|
|
PERF_SP_LM_BANK_CONFLICTS = 64,
|
|
};
|
|
|
|
enum a5xx_rb_perfcounter_select {
|
|
PERF_RB_BUSY_CYCLES = 0,
|
|
PERF_RB_STALL_CYCLES_CCU = 1,
|
|
PERF_RB_STALL_CYCLES_HLSQ = 2,
|
|
PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
|
|
PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
|
|
PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
|
|
PERF_RB_STARVE_CYCLES_SP = 6,
|
|
PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
|
|
PERF_RB_STARVE_CYCLES_CCU = 8,
|
|
PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
|
|
PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
|
|
PERF_RB_Z_WORKLOAD = 11,
|
|
PERF_RB_HLSQ_ACTIVE = 12,
|
|
PERF_RB_Z_READ = 13,
|
|
PERF_RB_Z_WRITE = 14,
|
|
PERF_RB_C_READ = 15,
|
|
PERF_RB_C_WRITE = 16,
|
|
PERF_RB_TOTAL_PASS = 17,
|
|
PERF_RB_Z_PASS = 18,
|
|
PERF_RB_Z_FAIL = 19,
|
|
PERF_RB_S_FAIL = 20,
|
|
PERF_RB_BLENDED_FXP_COMPONENTS = 21,
|
|
PERF_RB_BLENDED_FP16_COMPONENTS = 22,
|
|
RB_RESERVED = 23,
|
|
PERF_RB_2D_ALIVE_CYCLES = 24,
|
|
PERF_RB_2D_STALL_CYCLES_A2D = 25,
|
|
PERF_RB_2D_STARVE_CYCLES_SRC = 26,
|
|
PERF_RB_2D_STARVE_CYCLES_SP = 27,
|
|
PERF_RB_2D_STARVE_CYCLES_DST = 28,
|
|
PERF_RB_2D_VALID_PIXELS = 29,
|
|
};
|
|
|
|
enum a5xx_rb_samples_perfcounter_select {
|
|
TOTAL_SAMPLES = 0,
|
|
ZPASS_SAMPLES = 1,
|
|
ZFAIL_SAMPLES = 2,
|
|
SFAIL_SAMPLES = 3,
|
|
};
|
|
|
|
enum a5xx_vsc_perfcounter_select {
|
|
PERF_VSC_BUSY_CYCLES = 0,
|
|
PERF_VSC_WORKING_CYCLES = 1,
|
|
PERF_VSC_STALL_CYCLES_UCHE = 2,
|
|
PERF_VSC_EOT_NUM = 3,
|
|
};
|
|
|
|
enum a5xx_ccu_perfcounter_select {
|
|
PERF_CCU_BUSY_CYCLES = 0,
|
|
PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
|
|
PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
|
|
PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
|
|
PERF_CCU_DEPTH_BLOCKS = 4,
|
|
PERF_CCU_COLOR_BLOCKS = 5,
|
|
PERF_CCU_DEPTH_BLOCK_HIT = 6,
|
|
PERF_CCU_COLOR_BLOCK_HIT = 7,
|
|
PERF_CCU_PARTIAL_BLOCK_READ = 8,
|
|
PERF_CCU_GMEM_READ = 9,
|
|
PERF_CCU_GMEM_WRITE = 10,
|
|
PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
|
|
PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
|
|
PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
|
|
PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
|
|
PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
|
|
PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
|
|
PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
|
|
PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
|
|
PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
|
|
PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
|
|
PERF_CCU_2D_BUSY_CYCLES = 21,
|
|
PERF_CCU_2D_RD_REQ = 22,
|
|
PERF_CCU_2D_WR_REQ = 23,
|
|
PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
|
|
PERF_CCU_2D_PIXELS = 25,
|
|
};
|
|
|
|
enum a5xx_cmp_perfcounter_select {
|
|
PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
|
|
PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
|
|
PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
|
|
PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
|
|
PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
|
|
PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
|
|
PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
|
|
PERF_CMPDECMP_VBIF_READ_DATA = 7,
|
|
PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
|
|
PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
|
|
PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
|
|
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
|
|
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
|
|
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
|
|
PERF_CMPDECMP_2D_RD_DATA = 22,
|
|
PERF_CMPDECMP_2D_WR_DATA = 23,
|
|
};
|
|
|
|
enum a5xx_vbif_perfcounter_select {
|
|
AXI_READ_REQUESTS_ID_0 = 0,
|
|
AXI_READ_REQUESTS_ID_1 = 1,
|
|
AXI_READ_REQUESTS_ID_2 = 2,
|
|
AXI_READ_REQUESTS_ID_3 = 3,
|
|
AXI_READ_REQUESTS_ID_4 = 4,
|
|
AXI_READ_REQUESTS_ID_5 = 5,
|
|
AXI_READ_REQUESTS_ID_6 = 6,
|
|
AXI_READ_REQUESTS_ID_7 = 7,
|
|
AXI_READ_REQUESTS_ID_8 = 8,
|
|
AXI_READ_REQUESTS_ID_9 = 9,
|
|
AXI_READ_REQUESTS_ID_10 = 10,
|
|
AXI_READ_REQUESTS_ID_11 = 11,
|
|
AXI_READ_REQUESTS_ID_12 = 12,
|
|
AXI_READ_REQUESTS_ID_13 = 13,
|
|
AXI_READ_REQUESTS_ID_14 = 14,
|
|
AXI_READ_REQUESTS_ID_15 = 15,
|
|
AXI0_READ_REQUESTS_TOTAL = 16,
|
|
AXI1_READ_REQUESTS_TOTAL = 17,
|
|
AXI2_READ_REQUESTS_TOTAL = 18,
|
|
AXI3_READ_REQUESTS_TOTAL = 19,
|
|
AXI_READ_REQUESTS_TOTAL = 20,
|
|
AXI_WRITE_REQUESTS_ID_0 = 21,
|
|
AXI_WRITE_REQUESTS_ID_1 = 22,
|
|
AXI_WRITE_REQUESTS_ID_2 = 23,
|
|
AXI_WRITE_REQUESTS_ID_3 = 24,
|
|
AXI_WRITE_REQUESTS_ID_4 = 25,
|
|
AXI_WRITE_REQUESTS_ID_5 = 26,
|
|
AXI_WRITE_REQUESTS_ID_6 = 27,
|
|
AXI_WRITE_REQUESTS_ID_7 = 28,
|
|
AXI_WRITE_REQUESTS_ID_8 = 29,
|
|
AXI_WRITE_REQUESTS_ID_9 = 30,
|
|
AXI_WRITE_REQUESTS_ID_10 = 31,
|
|
AXI_WRITE_REQUESTS_ID_11 = 32,
|
|
AXI_WRITE_REQUESTS_ID_12 = 33,
|
|
AXI_WRITE_REQUESTS_ID_13 = 34,
|
|
AXI_WRITE_REQUESTS_ID_14 = 35,
|
|
AXI_WRITE_REQUESTS_ID_15 = 36,
|
|
AXI0_WRITE_REQUESTS_TOTAL = 37,
|
|
AXI1_WRITE_REQUESTS_TOTAL = 38,
|
|
AXI2_WRITE_REQUESTS_TOTAL = 39,
|
|
AXI3_WRITE_REQUESTS_TOTAL = 40,
|
|
AXI_WRITE_REQUESTS_TOTAL = 41,
|
|
AXI_TOTAL_REQUESTS = 42,
|
|
AXI_READ_DATA_BEATS_ID_0 = 43,
|
|
AXI_READ_DATA_BEATS_ID_1 = 44,
|
|
AXI_READ_DATA_BEATS_ID_2 = 45,
|
|
AXI_READ_DATA_BEATS_ID_3 = 46,
|
|
AXI_READ_DATA_BEATS_ID_4 = 47,
|
|
AXI_READ_DATA_BEATS_ID_5 = 48,
|
|
AXI_READ_DATA_BEATS_ID_6 = 49,
|
|
AXI_READ_DATA_BEATS_ID_7 = 50,
|
|
AXI_READ_DATA_BEATS_ID_8 = 51,
|
|
AXI_READ_DATA_BEATS_ID_9 = 52,
|
|
AXI_READ_DATA_BEATS_ID_10 = 53,
|
|
AXI_READ_DATA_BEATS_ID_11 = 54,
|
|
AXI_READ_DATA_BEATS_ID_12 = 55,
|
|
AXI_READ_DATA_BEATS_ID_13 = 56,
|
|
AXI_READ_DATA_BEATS_ID_14 = 57,
|
|
AXI_READ_DATA_BEATS_ID_15 = 58,
|
|
AXI0_READ_DATA_BEATS_TOTAL = 59,
|
|
AXI1_READ_DATA_BEATS_TOTAL = 60,
|
|
AXI2_READ_DATA_BEATS_TOTAL = 61,
|
|
AXI3_READ_DATA_BEATS_TOTAL = 62,
|
|
AXI_READ_DATA_BEATS_TOTAL = 63,
|
|
AXI_WRITE_DATA_BEATS_ID_0 = 64,
|
|
AXI_WRITE_DATA_BEATS_ID_1 = 65,
|
|
AXI_WRITE_DATA_BEATS_ID_2 = 66,
|
|
AXI_WRITE_DATA_BEATS_ID_3 = 67,
|
|
AXI_WRITE_DATA_BEATS_ID_4 = 68,
|
|
AXI_WRITE_DATA_BEATS_ID_5 = 69,
|
|
AXI_WRITE_DATA_BEATS_ID_6 = 70,
|
|
AXI_WRITE_DATA_BEATS_ID_7 = 71,
|
|
AXI_WRITE_DATA_BEATS_ID_8 = 72,
|
|
AXI_WRITE_DATA_BEATS_ID_9 = 73,
|
|
AXI_WRITE_DATA_BEATS_ID_10 = 74,
|
|
AXI_WRITE_DATA_BEATS_ID_11 = 75,
|
|
AXI_WRITE_DATA_BEATS_ID_12 = 76,
|
|
AXI_WRITE_DATA_BEATS_ID_13 = 77,
|
|
AXI_WRITE_DATA_BEATS_ID_14 = 78,
|
|
AXI_WRITE_DATA_BEATS_ID_15 = 79,
|
|
AXI0_WRITE_DATA_BEATS_TOTAL = 80,
|
|
AXI1_WRITE_DATA_BEATS_TOTAL = 81,
|
|
AXI2_WRITE_DATA_BEATS_TOTAL = 82,
|
|
AXI3_WRITE_DATA_BEATS_TOTAL = 83,
|
|
AXI_WRITE_DATA_BEATS_TOTAL = 84,
|
|
AXI_DATA_BEATS_TOTAL = 85,
|
|
};
|
|
|
|
enum a5xx_tex_filter {
|
|
A5XX_TEX_NEAREST = 0,
|
|
A5XX_TEX_LINEAR = 1,
|
|
A5XX_TEX_ANISO = 2,
|
|
};
|
|
|
|
enum a5xx_tex_clamp {
|
|
A5XX_TEX_REPEAT = 0,
|
|
A5XX_TEX_CLAMP_TO_EDGE = 1,
|
|
A5XX_TEX_MIRROR_REPEAT = 2,
|
|
A5XX_TEX_CLAMP_TO_BORDER = 3,
|
|
A5XX_TEX_MIRROR_CLAMP = 4,
|
|
};
|
|
|
|
enum a5xx_tex_aniso {
|
|
A5XX_TEX_ANISO_1 = 0,
|
|
A5XX_TEX_ANISO_2 = 1,
|
|
A5XX_TEX_ANISO_4 = 2,
|
|
A5XX_TEX_ANISO_8 = 3,
|
|
A5XX_TEX_ANISO_16 = 4,
|
|
};
|
|
|
|
enum a5xx_tex_swiz {
|
|
A5XX_TEX_X = 0,
|
|
A5XX_TEX_Y = 1,
|
|
A5XX_TEX_Z = 2,
|
|
A5XX_TEX_W = 3,
|
|
A5XX_TEX_ZERO = 4,
|
|
A5XX_TEX_ONE = 5,
|
|
};
|
|
|
|
enum a5xx_tex_type {
|
|
A5XX_TEX_1D = 0,
|
|
A5XX_TEX_2D = 1,
|
|
A5XX_TEX_CUBE = 2,
|
|
A5XX_TEX_3D = 3,
|
|
};
|
|
|
|
#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
|
|
#define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
|
|
#define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
|
|
#define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
|
|
#define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
|
|
#define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
|
|
#define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
|
|
#define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
|
|
#define A5XX_INT0_CP_SW 0x00000100
|
|
#define A5XX_INT0_CP_HW_ERROR 0x00000200
|
|
#define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
|
|
#define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
|
|
#define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
|
|
#define A5XX_INT0_CP_IB2 0x00002000
|
|
#define A5XX_INT0_CP_IB1 0x00004000
|
|
#define A5XX_INT0_CP_RB 0x00008000
|
|
#define A5XX_INT0_CP_UNUSED_1 0x00010000
|
|
#define A5XX_INT0_CP_RB_DONE_TS 0x00020000
|
|
#define A5XX_INT0_CP_WT_DONE_TS 0x00040000
|
|
#define A5XX_INT0_UNKNOWN_1 0x00080000
|
|
#define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
|
|
#define A5XX_INT0_UNUSED_2 0x00200000
|
|
#define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
|
|
#define A5XX_INT0_MISC_HANG_DETECT 0x00800000
|
|
#define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
|
|
#define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
|
|
#define A5XX_INT0_DEBBUS_INTR_0 0x04000000
|
|
#define A5XX_INT0_DEBBUS_INTR_1 0x08000000
|
|
#define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
|
|
#define A5XX_INT0_GPMU_FIRMWARE 0x20000000
|
|
#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
|
|
#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
|
|
#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
|
|
#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
|
|
#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
|
|
#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
|
|
#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
|
|
#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
|
|
#define REG_A5XX_CP_RB_BASE 0x00000800
|
|
|
|
#define REG_A5XX_CP_RB_BASE_HI 0x00000801
|
|
|
|
#define REG_A5XX_CP_RB_CNTL 0x00000802
|
|
|
|
#define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
|
|
|
|
#define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
|
|
|
|
#define REG_A5XX_CP_RB_RPTR 0x00000806
|
|
|
|
#define REG_A5XX_CP_RB_WPTR 0x00000807
|
|
|
|
#define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
|
|
|
|
#define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
|
|
|
|
#define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
|
|
|
|
#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
|
|
|
|
#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
|
|
|
|
#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
|
|
|
|
#define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
|
|
|
|
#define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
|
|
|
|
#define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
|
|
|
|
#define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
|
|
|
|
#define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
|
|
|
|
#define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
|
|
|
|
#define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
|
|
|
|
#define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
|
|
|
|
#define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
|
|
|
|
#define REG_A5XX_CP_MERCIU_SIZE 0x00000826
|
|
|
|
#define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
|
|
|
|
#define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
|
|
|
|
#define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
|
|
|
|
#define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
|
|
|
|
#define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
|
|
|
|
#define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
|
|
|
|
#define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
|
|
|
|
#define REG_A5XX_CP_CNTL 0x00000831
|
|
|
|
#define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
|
|
|
|
#define REG_A5XX_CP_CHICKEN_DBG 0x00000833
|
|
|
|
#define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
|
|
|
|
#define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
|
|
|
|
#define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
|
|
|
|
#define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
|
|
|
|
#define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
|
|
|
|
#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
|
|
|
|
#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
|
|
|
|
#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
|
|
|
|
#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
|
|
|
|
#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
|
|
|
|
#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
|
|
|
|
#define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
|
|
|
|
#define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
|
|
|
|
#define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
|
|
|
|
#define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
|
|
|
|
#define REG_A5XX_CP_HW_FAULT 0x00000b1a
|
|
|
|
#define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
|
|
|
|
#define REG_A5XX_CP_IB1_BASE 0x00000b1f
|
|
|
|
#define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
|
|
|
|
#define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
|
|
|
|
#define REG_A5XX_CP_IB2_BASE 0x00000b22
|
|
|
|
#define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
|
|
|
|
#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
|
|
|
|
static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
|
|
#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
|
|
#define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
|
|
static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
|
|
}
|
|
#define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
|
|
#define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
|
|
static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
|
|
}
|
|
#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
|
|
#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
|
|
|
|
#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
|
|
|
|
#define REG_A5XX_CP_AHB_FAULT 0x00000b1b
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
|
|
|
|
#define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
|
|
|
|
#define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
|
|
|
|
#define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
|
|
|
|
#define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
|
|
|
|
#define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
|
|
|
|
#define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
|
|
|
|
#define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
|
|
|
|
#define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
|
|
|
|
#define REG_A5XX_RBBM_INT_0_MASK 0x00000038
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
|
|
#define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
|
|
#define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
|
|
#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
|
|
#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
|
|
#define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
|
|
#define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
|
|
#define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
|
|
#define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
|
|
#define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
|
|
#define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
|
|
#define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
|
|
#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
|
|
#define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
|
|
#define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
|
|
#define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
|
|
#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
|
|
#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
|
|
#define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
|
|
#define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
|
|
#define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
|
|
#define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
|
|
|
|
#define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
|
|
|
|
#define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
|
|
|
|
#define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
|
|
|
|
#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
|
|
|
|
#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
|
|
|
|
#define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
|
|
|
|
#define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
|
|
|
|
#define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
|
|
|
|
#define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
|
|
|
|
#define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
|
|
|
|
#define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
|
|
|
|
#define REG_A5XX_RBBM_AHB_CMD 0x00000096
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
|
|
|
|
#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
|
|
|
|
#define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
|
|
|
|
#define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
|
|
|
|
#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
|
|
|
|
#define REG_A5XX_RBBM_STATUS 0x000004f5
|
|
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
|
|
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
|
|
#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
|
|
#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
|
|
#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
|
|
#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
|
|
#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
|
|
#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
|
|
#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
|
|
#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
|
|
#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
|
|
#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
|
|
#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
|
|
#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
|
|
#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
|
|
#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
|
|
#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
|
|
#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
|
|
#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
|
|
#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
|
|
#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
|
|
#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
|
|
#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
|
|
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
|
|
#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
|
|
#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
|
|
#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
|
|
#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
|
|
#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
|
|
#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
|
|
#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
|
|
#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
|
|
|
|
#define REG_A5XX_RBBM_STATUS3 0x00000530
|
|
|
|
#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
|
|
|
|
#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
|
|
|
|
#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
|
|
|
|
#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
|
|
|
|
#define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
|
|
|
|
#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
|
|
|
|
#define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
|
|
|
|
#define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
|
|
|
|
#define REG_A5XX_RBBM_ISDB_CNT 0x00000533
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
|
|
|
|
#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
|
|
|
|
#define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
|
|
#define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
|
|
#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
|
|
static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
|
|
}
|
|
#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
|
|
#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
|
|
static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
|
|
|
|
#define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
|
|
|
|
#define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
|
|
|
|
#define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
|
|
|
|
static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
|
|
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
|
|
}
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
|
|
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
|
|
}
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
|
|
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
|
|
}
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
|
|
#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
|
|
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
|
|
|
|
#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
|
|
|
|
#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
|
|
|
|
#define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
|
|
#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
|
|
#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
|
|
static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
|
|
}
|
|
#define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
|
|
#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
|
|
static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
|
|
|
|
#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
|
|
|
|
#define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
|
|
|
|
#define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
|
|
|
|
#define REG_A5XX_RB_MODE_CNTL 0x00000cc6
|
|
|
|
#define REG_A5XX_RB_CCU_CNTL 0x00000cc7
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
|
|
|
|
#define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
|
|
|
|
#define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
|
|
|
|
#define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
|
|
|
|
#define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
|
|
|
|
#define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
|
|
|
|
#define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
|
|
|
|
#define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
|
|
|
|
#define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
|
|
|
|
#define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
|
|
#define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
|
|
|
|
#define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
|
|
|
|
#define REG_A5XX_PC_MODE_CNTL 0x00000d02
|
|
|
|
#define REG_A5XX_UNKNOWN_0D08 0x00000d08
|
|
|
|
#define REG_A5XX_UNKNOWN_0D09 0x00000d09
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
|
|
|
|
#define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
|
|
|
|
#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
|
|
|
|
#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
|
|
|
|
#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
|
|
|
|
#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
|
|
|
|
#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
|
|
|
|
#define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
|
|
|
|
#define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
|
|
|
|
#define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
|
|
|
|
#define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
|
|
|
|
#define REG_A5XX_VFD_MODE_CNTL 0x00000e42
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
|
|
|
|
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
|
|
|
|
#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
|
|
|
|
#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
|
|
|
|
#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
|
|
#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
|
|
|
|
#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
|
|
|
|
#define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
|
|
|
|
#define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
|
|
|
|
#define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
|
|
|
|
#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
|
|
|
|
#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
|
|
|
|
#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
|
|
|
|
#define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
|
|
|
|
#define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
|
|
|
|
#define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
|
|
|
|
#define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
|
|
|
|
#define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
|
|
|
|
#define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
|
|
|
|
#define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
|
|
|
|
#define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
|
|
|
|
#define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
|
|
|
|
#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
|
|
|
|
#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
|
|
|
|
#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
|
|
|
|
#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
|
|
|
|
#define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
|
|
|
|
#define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
|
|
|
|
#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
|
|
|
|
#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
|
|
|
|
#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
|
|
|
|
#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
|
|
|
|
#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
|
|
|
|
#define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
|
|
|
|
#define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
|
|
|
|
#define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
|
|
|
|
#define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
|
|
|
|
#define REG_A5XX_SP_MODE_CNTL 0x00000ec2
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
|
|
|
|
#define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
|
|
|
|
#define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
|
|
|
|
#define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
|
|
|
|
#define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
|
|
|
|
#define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
|
|
|
|
#define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
|
|
|
|
#define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
|
|
|
|
#define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
|
|
|
|
#define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
|
|
|
|
#define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
|
|
|
|
#define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
|
|
|
|
#define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
|
|
|
|
#define REG_A5XX_VBIF_VERSION 0x00003000
|
|
|
|
#define REG_A5XX_VBIF_CLKON 0x00003001
|
|
|
|
#define REG_A5XX_VBIF_ABIT_SORT 0x00003028
|
|
|
|
#define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
|
|
|
|
#define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
|
|
|
|
#define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
|
|
|
|
#define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
|
|
|
|
#define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
|
|
|
|
#define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
|
|
|
|
#define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
|
|
|
|
#define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
|
|
|
|
#define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
|
|
|
|
#define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
|
|
|
|
#define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
|
|
|
|
#define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
|
|
|
|
#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
|
|
|
|
#define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
|
|
|
|
#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
|
|
|
|
#define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
|
|
|
|
#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
|
|
|
|
#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
|
|
|
|
#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
|
|
|
|
#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
|
|
|
|
#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
|
|
#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
|
|
|
|
#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
|
|
#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
|
|
|
|
#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
|
|
|
|
#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
|
|
|
|
#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
|
|
|
|
#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
|
|
|
|
#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
|
|
|
|
#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
|
|
|
|
#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
|
|
|
|
#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
|
|
|
|
#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
|
|
|
|
#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
|
|
|
|
#define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
|
|
|
|
#define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
|
|
|
|
#define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
|
|
|
|
#define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
|
|
|
|
#define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
|
|
|
|
#define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
|
|
|
|
#define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
|
|
|
|
#define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
|
|
|
|
#define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
|
|
|
|
#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
|
|
|
|
#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
|
|
|
|
#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
|
|
|
|
#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
|
|
|
|
#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
|
|
|
|
#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
|
|
|
|
#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
|
|
|
|
#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
|
|
|
|
#define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
|
|
|
|
#define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
|
|
|
|
#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
|
|
|
|
#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
|
|
|
|
#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
|
|
|
|
#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
|
|
|
|
#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
|
|
|
|
#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
|
|
|
|
#define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
|
|
|
|
#define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
|
|
|
|
#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
|
|
|
|
#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
|
|
|
|
#define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
|
|
|
|
#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
|
|
|
|
#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
|
|
|
|
#define REG_A5XX_GDPM_CONFIG1 0x0000b80c
|
|
|
|
#define REG_A5XX_GDPM_CONFIG2 0x0000b80d
|
|
|
|
#define REG_A5XX_GDPM_INT_EN 0x0000b80f
|
|
|
|
#define REG_A5XX_GDPM_INT_MASK 0x0000b811
|
|
|
|
#define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
|
|
|
|
#define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
|
|
|
|
#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
|
|
|
|
#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
|
|
|
|
#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
|
|
|
|
#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
|
|
|
|
#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
|
|
|
|
#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
|
|
|
|
#define REG_A5XX_UNKNOWN_E001 0x0000e001
|
|
|
|
#define REG_A5XX_UNKNOWN_E004 0x0000e004
|
|
|
|
#define REG_A5XX_GRAS_CNTL 0x0000e005
|
|
#define A5XX_GRAS_CNTL_VARYING 0x00000001
|
|
#define A5XX_GRAS_CNTL_UNK3 0x00000008
|
|
#define A5XX_GRAS_CNTL_XCOORD 0x00000040
|
|
#define A5XX_GRAS_CNTL_YCOORD 0x00000080
|
|
#define A5XX_GRAS_CNTL_ZCOORD 0x00000100
|
|
#define A5XX_GRAS_CNTL_WCOORD 0x00000200
|
|
|
|
#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
|
|
#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
|
|
#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
|
|
}
|
|
#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
|
|
#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
|
|
static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
|
|
#define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
|
|
#define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
|
|
#define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
|
|
#define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
|
|
#define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
|
|
#define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
|
|
#define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
|
|
#define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
|
|
#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
|
|
#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
|
|
#define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
|
|
#define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SU_CNTL 0x0000e090
|
|
#define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
|
|
#define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
|
|
#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
|
|
#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
|
|
#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
|
|
static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
|
|
{
|
|
return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
|
|
}
|
|
#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
|
|
#define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
|
|
|
|
#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
|
|
#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
|
|
#define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
|
|
{
|
|
return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
|
|
}
|
|
#define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
|
|
#define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
|
|
static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
|
|
{
|
|
return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
|
|
#define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
|
|
#define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
|
|
{
|
|
return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_UNKNOWN_E093 0x0000e093
|
|
|
|
#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
|
|
#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
|
|
#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
|
|
|
|
#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
|
|
#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
|
|
#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
|
|
#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
|
|
#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
|
|
#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
|
|
#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
|
|
#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
|
|
#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
|
|
|
|
#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
|
|
#define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
|
|
#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
|
|
|
|
#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
|
|
|
|
#define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
|
|
#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
|
|
#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
#define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
|
|
|
|
#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
|
|
|
|
#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
|
|
}
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
|
|
static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
|
|
}
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
|
|
#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
|
|
static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
|
|
}
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
|
|
static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
|
|
}
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
|
|
#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
|
|
static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
|
|
}
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
|
|
static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
|
|
}
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
|
|
#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
|
|
static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
|
|
#define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
|
|
#define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
|
|
#define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
|
|
|
|
#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
|
|
|
|
#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
|
|
|
|
#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
|
|
#define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
|
|
#define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
|
|
|
|
#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
|
|
|
|
#define REG_A5XX_RB_CNTL 0x0000e140
|
|
#define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
|
|
#define A5XX_RB_CNTL_WIDTH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
|
|
}
|
|
#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
|
|
#define A5XX_RB_CNTL_HEIGHT__SHIFT 9
|
|
static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
|
|
}
|
|
#define A5XX_RB_CNTL_BYPASS 0x00020000
|
|
|
|
#define REG_A5XX_RB_RENDER_CNTL 0x0000e141
|
|
#define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
|
|
#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
|
|
#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
|
|
#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
|
|
#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
|
|
#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
|
|
#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
|
|
static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
|
|
#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
|
|
static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
|
|
#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
|
|
#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
|
|
|
|
#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
|
|
#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
|
|
#define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
|
|
#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
|
|
#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
|
|
#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
|
|
#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
|
|
|
|
#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
|
|
#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
|
|
|
|
#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
|
|
#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
|
|
#define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
|
|
}
|
|
#define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
|
|
|
|
#define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
|
|
}
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
|
|
#define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
|
|
static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
|
|
#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
|
|
#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
|
|
#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
|
|
#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
|
|
static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
|
|
static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
|
|
static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
|
|
static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
|
|
static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
|
|
static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
|
|
#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
|
|
static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
|
|
#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
|
|
#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
|
|
static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
|
|
#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
|
|
static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
#define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
|
|
#define A5XX_RB_MRT_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_MRT_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
|
|
#define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
|
|
|
|
#define REG_A5XX_RB_BLEND_RED 0x0000e1a0
|
|
#define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
|
|
#define A5XX_RB_BLEND_RED_UINT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
|
|
#define A5XX_RB_BLEND_RED_SINT__SHIFT 8
|
|
static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
|
|
#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
|
static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
|
|
#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
|
|
#define A5XX_RB_BLEND_RED_F32__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
|
|
#define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
|
|
#define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
|
|
#define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
|
|
static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
|
|
#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
|
static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
|
|
#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
|
|
#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
|
|
#define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
|
|
#define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
|
|
#define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
|
|
static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
|
|
#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
|
static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
|
|
#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
|
|
#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
|
|
#define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
|
|
#define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
|
|
#define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
|
|
static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
|
|
#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
|
static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
|
|
#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
|
|
#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
|
|
{
|
|
return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
|
|
#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
|
|
#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
|
|
static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
|
|
}
|
|
#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
|
|
#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
|
|
#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
|
|
static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
|
|
#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
|
|
#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
|
|
}
|
|
#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
|
|
#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
|
|
#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
|
|
static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
|
|
#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
|
|
#define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
|
|
|
|
#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
|
|
#define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
|
|
#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
|
|
#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
|
|
#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
|
|
static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
|
|
}
|
|
#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
|
|
|
|
#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
|
|
#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
|
|
#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
|
|
{
|
|
return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
|
|
|
|
#define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
|
|
|
|
#define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
|
|
#define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
|
|
#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
|
|
#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
|
|
#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
|
|
#define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
|
|
#define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
|
|
#define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
|
|
}
|
|
#define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
|
|
#define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
|
|
}
|
|
#define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
|
|
#define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
|
|
}
|
|
#define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
|
|
#define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
|
|
}
|
|
#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
|
|
#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
|
|
}
|
|
#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
|
|
#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
|
|
}
|
|
#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
|
|
#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
|
|
}
|
|
#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
|
|
#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
|
|
static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
|
|
#define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
|
|
|
|
#define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
|
|
|
|
#define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
|
|
|
|
#define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
|
|
#define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_STENCIL_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
|
|
#define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
|
|
#define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
|
|
#define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
|
|
static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
|
|
}
|
|
#define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
|
|
#define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
|
|
static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
|
|
}
|
|
#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
|
|
#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
|
|
static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7
|
|
|
|
#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
|
|
#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
|
|
#define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
|
|
static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
|
|
}
|
|
#define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
|
|
#define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
|
|
static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
|
|
#define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
|
|
|
|
#define REG_A5XX_RB_BLIT_CNTL 0x0000e210
|
|
#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
|
|
#define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
|
|
{
|
|
return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
|
|
#define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
|
|
#define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
|
|
static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
|
|
}
|
|
#define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
|
|
#define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
|
|
static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
|
|
#define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
|
|
#define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
|
|
static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
|
|
}
|
|
#define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
|
|
#define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
|
|
static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
|
|
|
|
#define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
|
|
|
|
#define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
|
|
|
|
#define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
|
|
#define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
|
|
#define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
|
|
|
|
#define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
|
|
|
|
#define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
|
|
|
|
#define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
|
|
|
|
#define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
|
|
#define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
|
|
#define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
|
|
#define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
|
|
static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
|
|
|
|
#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
|
|
|
|
#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
|
|
#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
|
|
#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
|
|
|
|
#define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
|
|
|
|
#define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
|
|
#define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
|
|
#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
|
|
|
|
#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
|
|
|
|
#define REG_A5XX_VPC_CNTL_0 0x0000e280
|
|
#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
|
|
#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
|
|
static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
|
|
}
|
|
#define A5XX_VPC_CNTL_0_VARYING 0x00000800
|
|
|
|
static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
|
|
|
|
#define REG_A5XX_UNKNOWN_E292 0x0000e292
|
|
|
|
#define REG_A5XX_UNKNOWN_E293 0x0000e293
|
|
|
|
static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
|
|
|
|
#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
|
|
|
|
#define REG_A5XX_UNKNOWN_E29A 0x0000e29a
|
|
|
|
#define REG_A5XX_VPC_PACK 0x0000e29d
|
|
#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
|
|
#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
|
|
static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
|
|
}
|
|
#define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
|
|
#define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
|
|
static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
|
|
|
|
#define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
|
|
#define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
|
|
#define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
|
|
#define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
|
|
#define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
|
|
#define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
|
|
|
|
#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
|
|
#define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
|
|
|
|
#define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
|
|
#define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
|
|
|
|
#define REG_A5XX_VPC_SO_PROG 0x0000e2a4
|
|
#define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
|
|
#define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
|
|
static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
|
|
}
|
|
#define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
|
|
#define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
|
|
static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
|
|
}
|
|
#define A5XX_VPC_SO_PROG_A_EN 0x00000800
|
|
#define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
|
|
#define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
|
|
static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
|
|
}
|
|
#define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
|
|
#define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
|
|
static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
|
|
}
|
|
#define A5XX_VPC_SO_PROG_B_EN 0x00800000
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
|
|
|
|
#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
|
|
#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
|
|
#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
|
|
static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
|
|
}
|
|
#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
|
|
|
|
#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
|
|
#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
|
|
|
|
#define REG_A5XX_PC_RASTER_CNTL 0x0000e388
|
|
|
|
#define REG_A5XX_UNKNOWN_E389 0x0000e389
|
|
|
|
#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
|
|
|
|
#define REG_A5XX_UNKNOWN_E38D 0x0000e38d
|
|
|
|
#define REG_A5XX_PC_GS_PARAM 0x0000e38e
|
|
|
|
#define REG_A5XX_PC_HS_PARAM 0x0000e38f
|
|
|
|
#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
|
|
|
|
#define REG_A5XX_VFD_CONTROL_0 0x0000e400
|
|
#define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
|
|
#define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
|
|
static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_VFD_CONTROL_1 0x0000e401
|
|
#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
|
|
#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
|
|
static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
|
|
}
|
|
#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
|
|
#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
|
|
static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_VFD_CONTROL_2 0x0000e402
|
|
|
|
#define REG_A5XX_VFD_CONTROL_3 0x0000e403
|
|
|
|
#define REG_A5XX_VFD_CONTROL_4 0x0000e404
|
|
|
|
#define REG_A5XX_VFD_CONTROL_5 0x0000e405
|
|
|
|
#define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
|
|
|
|
#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
|
|
|
|
static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
|
|
#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
|
|
#define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
|
|
static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
|
|
}
|
|
#define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
|
|
#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000
|
|
#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
|
|
static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
|
|
{
|
|
return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
|
|
}
|
|
#define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
|
|
#define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
|
|
|
|
static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
|
|
#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
|
|
#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
|
|
static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
|
|
}
|
|
#define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
|
|
#define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
|
|
static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
|
|
|
|
#define REG_A5XX_SP_SP_CNTL 0x0000e580
|
|
|
|
#define REG_A5XX_SP_VS_CONFIG 0x0000e584
|
|
#define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_SP_FS_CONFIG 0x0000e585
|
|
#define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_SP_HS_CONFIG 0x0000e586
|
|
#define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_SP_DS_CONFIG 0x0000e587
|
|
#define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_SP_GS_CONFIG 0x0000e588
|
|
#define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_SP_CS_CONFIG 0x0000e589
|
|
#define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
|
|
|
|
#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
|
|
|
|
#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
|
|
#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
|
#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
|
|
static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
|
#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
|
static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
|
#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
|
static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
|
|
#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
|
|
#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
|
|
#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
|
|
static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
|
|
#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
|
|
#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
|
|
static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
|
|
#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
|
|
#define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
|
|
static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
|
|
}
|
|
#define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
|
|
#define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
|
|
static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
|
|
}
|
|
#define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
|
|
#define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
|
|
static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
|
|
}
|
|
#define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
|
|
#define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
|
|
static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
|
static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
|
|
}
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
|
static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
|
|
}
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
|
static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
|
|
}
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
|
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
|
static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
|
|
|
|
#define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
|
|
|
|
#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
|
|
|
|
#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
|
|
#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
|
#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
|
|
static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
|
#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
|
static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
|
#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
|
static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
|
|
#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
|
|
#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
|
|
#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
|
|
static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
|
|
|
|
#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
|
|
|
|
#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
|
|
|
|
#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
|
|
#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
|
|
#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
|
|
|
|
#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
|
|
#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
|
|
#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
|
|
static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
|
|
}
|
|
#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
|
|
#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
|
|
static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
|
|
}
|
|
#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
|
|
#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
|
|
static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
|
|
#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
|
|
#define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
|
|
static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
|
|
}
|
|
#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
|
|
|
|
static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
|
|
#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|
{
|
|
return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
|
|
|
|
#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
|
|
|
|
#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
|
|
|
|
#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
|
|
|
|
#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
|
|
|
|
#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
|
|
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
|
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
|
|
static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
|
#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
|
static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
|
#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
|
static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
|
|
#define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
|
|
#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
|
|
#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
|
|
static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_UNKNOWN_E600 0x0000e600
|
|
|
|
#define REG_A5XX_UNKNOWN_E602 0x0000e602
|
|
|
|
#define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
|
|
|
|
#define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
|
|
|
|
#define REG_A5XX_UNKNOWN_E62B 0x0000e62b
|
|
|
|
#define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
|
|
|
|
#define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
|
|
|
|
#define REG_A5XX_UNKNOWN_E640 0x0000e640
|
|
|
|
#define REG_A5XX_UNKNOWN_E65B 0x0000e65b
|
|
|
|
#define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
|
|
|
|
#define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
|
|
|
|
#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
|
|
#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
|
|
#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
#define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
|
|
|
|
#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
|
|
|
|
#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
|
|
|
|
#define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
|
|
|
|
#define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
|
|
|
|
#define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
|
|
|
|
#define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
|
|
|
|
#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
|
|
|
|
#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
|
|
|
|
#define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
|
|
|
|
#define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
|
|
|
|
#define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
|
|
|
|
#define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
|
|
|
|
#define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
|
|
|
|
#define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
|
|
|
|
#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
|
|
|
|
#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
|
|
|
|
#define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
|
|
|
|
#define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
|
|
|
|
#define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
|
|
|
|
#define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
|
|
|
|
#define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
|
|
|
|
#define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
|
|
|
|
#define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
|
|
|
|
#define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
|
|
|
|
#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
|
|
|
|
#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
|
|
|
|
#define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
|
|
|
|
#define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
|
|
|
|
#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
|
|
|
|
#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
|
|
|
|
#define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
|
|
|
|
#define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
|
|
|
|
#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
|
|
|
|
#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
|
|
#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
|
|
#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
|
|
#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
|
|
static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
|
|
#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
|
|
#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
|
|
#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
|
|
#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
|
|
#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
|
|
#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
|
|
#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
|
|
#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
|
|
static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
|
|
#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
|
|
static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
|
|
|
|
#define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
|
|
#define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
|
|
#define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
|
|
#define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
|
|
#define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
|
|
#define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
|
|
#define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
|
|
#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
|
|
#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
|
|
#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
|
|
static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
|
|
#define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
|
|
#define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
|
|
#define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
|
|
#define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
|
|
#define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
|
|
#define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
|
|
#define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
|
|
#define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
|
|
#define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
|
|
#define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
|
|
#define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
|
|
#define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
|
|
#define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
|
|
#define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
|
|
#define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
|
|
#define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
|
|
#define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
|
|
#define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
|
|
static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
|
|
|
|
#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
|
|
|
|
#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
|
|
|
|
#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
|
|
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
|
|
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
|
|
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
|
|
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
|
|
#define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff
|
|
#define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
|
|
|
|
#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
|
|
#define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff
|
|
#define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
|
|
|
|
#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
|
|
#define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff
|
|
#define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
|
|
|
|
#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
|
|
#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
|
|
#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
|
|
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
|
|
#define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
|
|
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
|
|
#define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
|
|
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
|
|
}
|
|
#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
|
|
#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
|
|
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
|
|
|
|
#define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
|
|
|
|
#define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
|
|
|
|
#define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
|
|
|
|
#define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
|
|
|
|
#define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
|
|
|
|
#define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
|
|
|
|
#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
|
|
|
|
#define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
|
|
|
|
#define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
|
|
|
|
#define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
|
|
|
|
#define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
|
|
|
|
#define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
|
|
|
|
#define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
|
|
|
|
#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
|
|
|
|
#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
|
|
|
|
#define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
|
|
|
|
#define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
|
|
|
|
#define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
|
|
|
|
#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
|
|
|
|
#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
|
|
|
|
#define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
|
|
|
|
#define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
|
|
|
|
#define REG_A5XX_RB_2D_SRC_INFO 0x00002107
|
|
#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|
{
|
|
return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
|
|
#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
|
|
static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_2D_SRC_LO 0x00002108
|
|
|
|
#define REG_A5XX_RB_2D_SRC_HI 0x00002109
|
|
|
|
#define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
|
|
#define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
|
|
#define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
|
|
}
|
|
#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
|
|
#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
|
|
static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_2D_DST_INFO 0x00002110
|
|
#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|
{
|
|
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
|
|
#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
|
|
static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_2D_DST_LO 0x00002111
|
|
|
|
#define REG_A5XX_RB_2D_DST_HI 0x00002112
|
|
|
|
#define REG_A5XX_RB_2D_DST_SIZE 0x00002113
|
|
#define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
|
|
#define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
|
|
}
|
|
#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
|
|
#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
|
|
static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
|
|
|
|
#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
|
|
|
|
#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
|
|
|
|
#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
|
|
|
|
#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
|
|
#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|
{
|
|
return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
|
|
#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
|
|
static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
|
|
#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|
{
|
|
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
|
|
#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
|
|
static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_UNKNOWN_2100 0x00002100
|
|
|
|
#define REG_A5XX_UNKNOWN_2180 0x00002180
|
|
|
|
#define REG_A5XX_UNKNOWN_2184 0x00002184
|
|
|
|
#define REG_A5XX_TEX_SAMP_0 0x00000000
|
|
#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
|
|
#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
|
|
#define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
|
|
static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
|
|
#define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
|
|
static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
|
|
#define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
|
|
static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
|
|
#define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
|
|
static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
|
|
#define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
|
|
static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
|
|
#define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
|
|
static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
|
|
#define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
|
|
static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
|
|
{
|
|
return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_SAMP_1 0x00000001
|
|
#define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
|
|
#define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
|
|
static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
|
|
#define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
|
|
#define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
|
|
#define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
|
|
#define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
|
|
static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
|
|
{
|
|
return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
|
|
}
|
|
#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
|
|
#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
|
|
static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
|
|
{
|
|
return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_SAMP_2 0x00000002
|
|
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
|
|
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
|
|
static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_SAMP_3 0x00000003
|
|
|
|
#define REG_A5XX_TEX_CONST_0 0x00000000
|
|
#define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
|
|
#define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
|
|
static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_0_SRGB 0x00000004
|
|
#define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
|
|
#define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
|
|
static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
|
|
#define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
|
|
static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
|
|
#define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
|
|
static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
|
|
#define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
|
|
static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
|
|
#define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
|
|
static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
|
|
#define A5XX_TEX_CONST_0_FMT__SHIFT 22
|
|
static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
|
|
#define A5XX_TEX_CONST_0_SWAP__SHIFT 30
|
|
static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_CONST_1 0x00000001
|
|
#define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
|
|
#define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
|
|
static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
|
|
#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
|
|
static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_CONST_2 0x00000002
|
|
#define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
|
|
#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
|
|
static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
|
|
#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
|
|
static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
|
|
#define A5XX_TEX_CONST_2_TYPE__SHIFT 29
|
|
static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_CONST_3 0x00000003
|
|
#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
|
|
#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_3_FLAG 0x10000000
|
|
|
|
#define REG_A5XX_TEX_CONST_4 0x00000004
|
|
#define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
|
|
#define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
|
|
static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_CONST_5 0x00000005
|
|
#define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
|
|
#define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
|
|
static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
|
|
}
|
|
#define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
|
|
#define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
|
|
static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
|
|
{
|
|
return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
|
|
}
|
|
|
|
#define REG_A5XX_TEX_CONST_6 0x00000006
|
|
|
|
#define REG_A5XX_TEX_CONST_7 0x00000007
|
|
|
|
#define REG_A5XX_TEX_CONST_8 0x00000008
|
|
|
|
#define REG_A5XX_TEX_CONST_9 0x00000009
|
|
|
|
#define REG_A5XX_TEX_CONST_10 0x0000000a
|
|
|
|
#define REG_A5XX_TEX_CONST_11 0x0000000b
|
|
|
|
|
|
#endif /* A5XX_XML */
|