forked from Minki/linux
a65986824d
Instead of assuming that all rt3090 devices will have an eFuse EEPROM, do as the legacy Ralink driver, and detect at run-time whether an eFuse EEPROM is present. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Acked-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
182 lines
4.6 KiB
C
182 lines
4.6 KiB
C
/*
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Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the
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Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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Module: rt2800pci
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Abstract: Data structures and registers for the rt2800pci module.
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Supported chipsets: RT2800E & RT2800ED.
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*/
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#ifndef RT2800PCI_H
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#define RT2800PCI_H
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/*
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* PCI registers.
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*/
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/*
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* E2PROM_CSR: EEPROM control register.
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* RELOAD: Write 1 to reload eeprom content.
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* TYPE: 0: 93c46, 1:93c66.
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* LOAD_STATUS: 1:loading, 0:done.
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*/
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#define E2PROM_CSR 0x0004
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#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
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#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
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#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
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#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
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#define E2PROM_CSR_TYPE FIELD32(0x00000030)
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#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
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#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
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/*
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* Queue register offset macros
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*/
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#define TX_QUEUE_REG_OFFSET 0x10
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#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
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#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
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#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
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#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
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/*
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* EFUSE_CSR: RT3090 EEPROM
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*/
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#define EFUSE_CTRL 0x0580
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#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
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#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
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#define EFUSE_CTRL_KICK FIELD32(0x40000000)
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#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
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/*
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* EFUSE_DATA0
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*/
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#define EFUSE_DATA0 0x0590
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/*
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* EFUSE_DATA1
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*/
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#define EFUSE_DATA1 0x0594
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/*
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* EFUSE_DATA2
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*/
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#define EFUSE_DATA2 0x0598
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/*
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* EFUSE_DATA3
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*/
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#define EFUSE_DATA3 0x059c
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/*
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* 8051 firmware image.
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*/
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#define FIRMWARE_RT2860 "rt2860.bin"
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#define FIRMWARE_IMAGE_BASE 0x2000
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/*
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* DMA descriptor defines.
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*/
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#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
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#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
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/*
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* TX descriptor format for TX, PRIO and Beacon Ring.
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*/
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/*
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* Word0
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*/
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#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
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/*
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* Word1
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*/
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#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
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#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
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#define TXD_W1_BURST FIELD32(0x00008000)
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#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
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#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
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#define TXD_W1_DMA_DONE FIELD32(0x80000000)
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/*
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* Word2
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*/
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#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
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/*
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* Word3
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* WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
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* QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
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* 0:MGMT, 1:HCCA 2:EDCA
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*/
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#define TXD_W3_WIV FIELD32(0x01000000)
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#define TXD_W3_QSEL FIELD32(0x06000000)
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#define TXD_W3_TCO FIELD32(0x20000000)
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#define TXD_W3_UCO FIELD32(0x40000000)
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#define TXD_W3_ICO FIELD32(0x80000000)
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/*
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* RX descriptor format for RX Ring.
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*/
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/*
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* Word0
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*/
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#define RXD_W0_SDP0 FIELD32(0xffffffff)
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/*
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* Word1
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*/
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#define RXD_W1_SDL1 FIELD32(0x00003fff)
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#define RXD_W1_SDL0 FIELD32(0x3fff0000)
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#define RXD_W1_LS0 FIELD32(0x40000000)
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#define RXD_W1_DMA_DONE FIELD32(0x80000000)
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/*
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* Word2
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*/
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#define RXD_W2_SDP1 FIELD32(0xffffffff)
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/*
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* Word3
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* AMSDU: RX with 802.3 header, not 802.11 header.
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* DECRYPTED: This frame is being decrypted.
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*/
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#define RXD_W3_BA FIELD32(0x00000001)
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#define RXD_W3_DATA FIELD32(0x00000002)
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#define RXD_W3_NULLDATA FIELD32(0x00000004)
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#define RXD_W3_FRAG FIELD32(0x00000008)
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#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
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#define RXD_W3_MULTICAST FIELD32(0x00000020)
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#define RXD_W3_BROADCAST FIELD32(0x00000040)
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#define RXD_W3_MY_BSS FIELD32(0x00000080)
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#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
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#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
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#define RXD_W3_AMSDU FIELD32(0x00000800)
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#define RXD_W3_HTC FIELD32(0x00001000)
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#define RXD_W3_RSSI FIELD32(0x00002000)
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#define RXD_W3_L2PAD FIELD32(0x00004000)
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#define RXD_W3_AMPDU FIELD32(0x00008000)
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#define RXD_W3_DECRYPTED FIELD32(0x00010000)
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#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
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#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
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#endif /* RT2800PCI_H */
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