3c0e3abd5e
SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum. According to regular hierarchy of sprd dts, whale2.dtsi contains SoC peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff and sp9860g dts is for the board level. Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
72 lines
1.5 KiB
Plaintext
72 lines
1.5 KiB
Plaintext
/*
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* Spreadtrum Whale2 platform peripherals
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*
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* Copyright (C) 2016, Spreadtrum Communications Inc.
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ap-apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x70000000 0x10000000>;
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uart0: serial@0 {
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compatible = "sprd,sc9860-uart",
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"sprd,sc9836-uart";
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reg = <0x0 0x100>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ext_26m>;
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status = "disabled";
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};
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uart1: serial@100000 {
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compatible = "sprd,sc9860-uart",
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"sprd,sc9836-uart";
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reg = <0x100000 0x100>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ext_26m>;
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status = "disabled";
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};
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uart2: serial@200000 {
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compatible = "sprd,sc9860-uart",
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"sprd,sc9836-uart";
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reg = <0x200000 0x100>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ext_26m>;
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status = "disabled";
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};
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uart3: serial@300000 {
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compatible = "sprd,sc9860-uart",
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"sprd,sc9836-uart";
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reg = <0x300000 0x100>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ext_26m>;
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status = "disabled";
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};
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};
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};
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ext_26m: ext-26m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "ext_26m";
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};
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};
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