Tvrtko Ursulin a6358dda29 drm/i915/icl: Icelake interrupt register addresses and bits ... MMIO addresses and register definition for the new interrupt registers in Gen11. v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter) v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio) v4: Bikeshedding (Paulo). Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180109232336.11029-5-paulo.r.zanoni@intel.com		2018-01-19 18:05:54 -02:00
..
drm	drm/i915/icl: Icelake interrupt register addresses and bits	2018-01-19 18:05:54 -02:00
host1x	main drm pull request for v4.15	2017-11-15 20:42:10 -08:00
ipu-v3	fixes/cleanups for rc1, non-desktop flags for VR	2017-11-23 21:04:56 -10:00
vga	vgaarb: Factor out EFI and fallback default device selection	2017-10-18 10:04:56 +02:00
Makefile