Nikola Cornij 84c63d0409 drm/amd/display: Use the correct max downscaling value for DCN3.x family ... [why] As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The max downscaling limit value for DCN2.x is 250, which means it's calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167. [how] Set maximum downscaling limit to 167 for DCN3.x Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2021-05-19 17:59:06 -04:00
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dcn30_afmt.c	drm/amd/display: Move common speakersToChannels definition to hw_shared.h	2020-11-10 14:25:15 -05:00
dcn30_afmt.h	drm/amd/display: Move common speakersToChannels definition to hw_shared.h	2020-11-10 14:25:15 -05:00
dcn30_cm_common.c	drm/amd/display: Correct algorithm for reversed gamma	2021-03-23 23:32:36 -04:00
dcn30_cm_common.h	drm/amd/display: Add DCN3 DPP	2020-07-01 01:59:14 -04:00
dcn30_dccg.c
dcn30_dccg.h
dcn30_dio_link_encoder.c	drm/amd/display: add dcn30_link_encoder_validate_output_with_stream to header	2020-12-15 11:34:04 -05:00
dcn30_dio_link_encoder.h	drm/amd/display: add dcn30_link_encoder_validate_output_with_stream to header	2020-12-15 11:34:04 -05:00
dcn30_dio_stream_encoder.c	drm/amd/display: Synchronize displays with different timings	2021-02-22 18:05:48 -05:00
dcn30_dio_stream_encoder.h	drm/amd/display: Add missing reg mask for dcn3	2020-07-08 09:02:37 -04:00
dcn30_dpp_cm.c	drm/amd/display: Remove unnecessary conversion to bool	2021-03-03 10:51:11 -05:00
dcn30_dpp.c	drm/amd/display: Remove unnecessary conversion to bool	2021-03-23 23:37:19 -04:00
dcn30_dpp.h	drm/amd/display: Add DSCL memory low power support	2020-12-01 16:03:40 -05:00
dcn30_dwb_cm.c	drm/amd/display: Remove unnecessary conversion to bool	2021-03-23 23:37:23 -04:00
dcn30_dwb.c	drm/amd/display: Add DCN3 DWB	2020-07-01 01:59:14 -04:00
dcn30_dwb.h	drm/amd/display: Add DCN3 DWB	2020-07-01 01:59:14 -04:00
dcn30_hubbub.c	drm/amd/display: Copy WM values from set A to other sets in hw_init	2020-10-05 15:16:36 -04:00
dcn30_hubbub.h	drm/amd/display: Copy WM values from set A to other sets in hw_init	2020-10-05 15:16:36 -04:00
dcn30_hubp.c	drm/amd/display: Enable pflip interrupt upon pipe enable	2021-03-23 23:02:33 -04:00
dcn30_hubp.h	drm/amd/display: Add missing mask for DCN3	2021-04-09 16:53:05 -04:00
dcn30_hwseq.c	drm/amd/display: Align cursor cache address to 2KB	2021-03-23 23:03:12 -04:00
dcn30_hwseq.h	drm/amd/display: Old sequence for HUBP blank	2021-02-18 16:43:11 -05:00
dcn30_init.c	drm/amd/display: Add function and debugfs to dump DCC_EN bit	2021-04-09 16:52:03 -04:00
dcn30_init.h	drm/amd/display: Init function tables for DCN3	2020-07-01 01:59:15 -04:00
dcn30_mmhubbub.c	drm/amd/display: Add DCN3 MMHUBHUB	2020-07-01 01:59:14 -04:00
dcn30_mmhubbub.h	drm/amd/display: Add DCN3 MMHUBHUB	2020-07-01 01:59:14 -04:00
dcn30_mpc.c	drm/amd/display: Remove unnecessary conversion to bool	2021-03-23 23:31:14 -04:00
dcn30_mpc.h	drm/amd/display: Add MPC memory shutdown support for DCN3	2020-11-02 15:29:47 -05:00
dcn30_opp.h	drm/amd/display: Add DCN3 OPP header	2020-07-01 01:59:14 -04:00
dcn30_optc.c	drm/amd/display: enable HUBP blank behaviour	2021-01-13 23:44:28 -05:00
dcn30_optc.h	drm/amd/display: update dcn30_optc header with missing declarations	2020-09-15 17:52:42 -04:00
dcn30_resource.c	drm/amd/display: Use the correct max downscaling value for DCN3.x family	2021-05-19 17:59:06 -04:00
dcn30_resource.h	drm/amd/display: fix dcn3+ bw validation soc param update sequence	2021-03-23 23:33:32 -04:00
dcn30_vpg.c	drm/amd/display: Change to IMMEDIATE mode from FRAME mode	2020-12-08 23:04:12 -05:00
dcn30_vpg.h	drm/amd/display: Change to IMMEDIATE mode from FRAME mode	2020-12-08 23:04:12 -05:00
Makefile	amdgpu: fix clang build warning	2021-01-25 17:48:46 -05:00