forked from Minki/linux
a5ac1ead32
The cpu_div3 clock (cpu_in divided by 3) generates a signal with a duty cycle of 33%. The CPU clock however requires a clock signal with a duty cycle of 50% to run stable. cpu_div3 was observed to be problematic when cycling through all available CPU frequencies (with additional patches on top of this one) while running "stress --cpu 4" in the background. This caused sporadic hangs where the whole system would fully lock up. Amlogic's 3.10 kernel code also does not use the cpu_div3 clock either when changing the CPU clock. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181115224048.13511-3-martin.blumenstingl@googlemail.com |
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.. | ||
axg-aoclk.c | ||
axg-aoclk.h | ||
axg-audio.c | ||
axg-audio.h | ||
axg.c | ||
axg.h | ||
clk-mpll.c | ||
clk-phase.c | ||
clk-pll.c | ||
clk-regmap.c | ||
clk-regmap.h | ||
clk-triphase.c | ||
clkc-audio.h | ||
clkc.h | ||
gxbb-aoclk-32k.c | ||
gxbb-aoclk.c | ||
gxbb-aoclk.h | ||
gxbb.c | ||
gxbb.h | ||
Kconfig | ||
Makefile | ||
meson8b.c | ||
meson8b.h | ||
meson-aoclk.c | ||
meson-aoclk.h | ||
sclk-div.c | ||
vid-pll-div.c |