forked from Minki/linux
bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
316 lines
8.4 KiB
C
316 lines
8.4 KiB
C
/*
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* Copyright (C) 2008 Ilya Yanok, Emcraft Systems
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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/*
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* The FPGA supports 9 interrupt sources, which can be routed to 3
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* interrupt request lines of the MPIC. The line to be used can be
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* specified through the third cell of FDT property "interrupts".
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*/
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#define SOCRATES_FPGA_NUM_IRQS 9
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#define FPGA_PIC_IRQCFG (0x0)
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#define FPGA_PIC_IRQMASK(n) (0x4 + 0x4 * (n))
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#define SOCRATES_FPGA_IRQ_MASK ((1 << SOCRATES_FPGA_NUM_IRQS) - 1)
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struct socrates_fpga_irq_info {
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unsigned int irq_line;
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int type;
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};
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/*
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* Interrupt routing and type table
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*
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* IRQ_TYPE_NONE means the interrupt type is configurable,
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* otherwise it's fixed to the specified value.
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*/
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static struct socrates_fpga_irq_info fpga_irqs[SOCRATES_FPGA_NUM_IRQS] = {
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[0] = {0, IRQ_TYPE_NONE},
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[1] = {0, IRQ_TYPE_LEVEL_HIGH},
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[2] = {0, IRQ_TYPE_LEVEL_LOW},
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[3] = {0, IRQ_TYPE_NONE},
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[4] = {0, IRQ_TYPE_NONE},
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[5] = {0, IRQ_TYPE_NONE},
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[6] = {0, IRQ_TYPE_NONE},
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[7] = {0, IRQ_TYPE_NONE},
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[8] = {0, IRQ_TYPE_LEVEL_HIGH},
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};
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static DEFINE_RAW_SPINLOCK(socrates_fpga_pic_lock);
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static void __iomem *socrates_fpga_pic_iobase;
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static struct irq_domain *socrates_fpga_pic_irq_host;
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static unsigned int socrates_fpga_irqs[3];
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static inline uint32_t socrates_fpga_pic_read(int reg)
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{
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return in_be32(socrates_fpga_pic_iobase + reg);
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}
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static inline void socrates_fpga_pic_write(int reg, uint32_t val)
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{
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out_be32(socrates_fpga_pic_iobase + reg, val);
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}
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static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq)
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{
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uint32_t cause;
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unsigned long flags;
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int i;
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/* Check irq line routed to the MPIC */
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for (i = 0; i < 3; i++) {
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if (irq == socrates_fpga_irqs[i])
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break;
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}
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if (i == 3)
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return NO_IRQ;
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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cause = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(i));
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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for (i = SOCRATES_FPGA_NUM_IRQS - 1; i >= 0; i--) {
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if (cause >> (i + 16))
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break;
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}
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return irq_linear_revmap(socrates_fpga_pic_irq_host,
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(irq_hw_number_t)i);
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}
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static void socrates_fpga_pic_cascade(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int irq = irq_desc_get_irq(desc);
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unsigned int cascade_irq;
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/*
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* See if we actually have an interrupt, call generic handling code if
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* we do.
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*/
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cascade_irq = socrates_fpga_pic_get_irq(irq);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static void socrates_fpga_pic_ack(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int irq_line, hwirq = irqd_to_hwirq(d);
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uint32_t mask;
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irq_line = fpga_irqs[hwirq].irq_line;
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
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& SOCRATES_FPGA_IRQ_MASK;
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mask |= (1 << (hwirq + 16));
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask);
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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}
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static void socrates_fpga_pic_mask(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int hwirq = irqd_to_hwirq(d);
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int irq_line;
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u32 mask;
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irq_line = fpga_irqs[hwirq].irq_line;
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
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& SOCRATES_FPGA_IRQ_MASK;
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mask &= ~(1 << hwirq);
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask);
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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}
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static void socrates_fpga_pic_mask_ack(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int hwirq = irqd_to_hwirq(d);
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int irq_line;
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u32 mask;
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irq_line = fpga_irqs[hwirq].irq_line;
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
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& SOCRATES_FPGA_IRQ_MASK;
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mask &= ~(1 << hwirq);
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mask |= (1 << (hwirq + 16));
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask);
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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}
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static void socrates_fpga_pic_unmask(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int hwirq = irqd_to_hwirq(d);
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int irq_line;
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u32 mask;
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irq_line = fpga_irqs[hwirq].irq_line;
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
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& SOCRATES_FPGA_IRQ_MASK;
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mask |= (1 << hwirq);
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask);
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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}
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static void socrates_fpga_pic_eoi(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int hwirq = irqd_to_hwirq(d);
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int irq_line;
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u32 mask;
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irq_line = fpga_irqs[hwirq].irq_line;
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
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& SOCRATES_FPGA_IRQ_MASK;
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mask |= (1 << (hwirq + 16));
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask);
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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}
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static int socrates_fpga_pic_set_type(struct irq_data *d,
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unsigned int flow_type)
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{
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unsigned long flags;
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unsigned int hwirq = irqd_to_hwirq(d);
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int polarity;
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u32 mask;
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if (fpga_irqs[hwirq].type != IRQ_TYPE_NONE)
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return -EINVAL;
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switch (flow_type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_LEVEL_HIGH:
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polarity = 1;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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polarity = 0;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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mask = socrates_fpga_pic_read(FPGA_PIC_IRQCFG);
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if (polarity)
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mask |= (1 << hwirq);
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else
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mask &= ~(1 << hwirq);
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socrates_fpga_pic_write(FPGA_PIC_IRQCFG, mask);
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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return 0;
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}
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static struct irq_chip socrates_fpga_pic_chip = {
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.name = "FPGA-PIC",
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.irq_ack = socrates_fpga_pic_ack,
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.irq_mask = socrates_fpga_pic_mask,
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.irq_mask_ack = socrates_fpga_pic_mask_ack,
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.irq_unmask = socrates_fpga_pic_unmask,
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.irq_eoi = socrates_fpga_pic_eoi,
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.irq_set_type = socrates_fpga_pic_set_type,
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};
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static int socrates_fpga_pic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hwirq)
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{
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/* All interrupts are LEVEL sensitive */
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &socrates_fpga_pic_chip,
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handle_fasteoi_irq);
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return 0;
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}
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static int socrates_fpga_pic_host_xlate(struct irq_domain *h,
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struct device_node *ct, const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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struct socrates_fpga_irq_info *fpga_irq = &fpga_irqs[intspec[0]];
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*out_hwirq = intspec[0];
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if (fpga_irq->type == IRQ_TYPE_NONE) {
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/* type is configurable */
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if (intspec[1] != IRQ_TYPE_LEVEL_LOW &&
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intspec[1] != IRQ_TYPE_LEVEL_HIGH) {
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pr_warning("FPGA PIC: invalid irq type, "
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"setting default active low\n");
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*out_flags = IRQ_TYPE_LEVEL_LOW;
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} else {
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*out_flags = intspec[1];
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}
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} else {
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/* type is fixed */
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*out_flags = fpga_irq->type;
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}
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/* Use specified interrupt routing */
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if (intspec[2] <= 2)
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fpga_irq->irq_line = intspec[2];
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else
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pr_warning("FPGA PIC: invalid irq routing\n");
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return 0;
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}
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static const struct irq_domain_ops socrates_fpga_pic_host_ops = {
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.map = socrates_fpga_pic_host_map,
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.xlate = socrates_fpga_pic_host_xlate,
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};
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void socrates_fpga_pic_init(struct device_node *pic)
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{
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unsigned long flags;
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int i;
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/* Setup an irq_domain structure */
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socrates_fpga_pic_irq_host = irq_domain_add_linear(pic,
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SOCRATES_FPGA_NUM_IRQS, &socrates_fpga_pic_host_ops, NULL);
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if (socrates_fpga_pic_irq_host == NULL) {
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pr_err("FPGA PIC: Unable to allocate host\n");
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return;
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}
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for (i = 0; i < 3; i++) {
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socrates_fpga_irqs[i] = irq_of_parse_and_map(pic, i);
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if (socrates_fpga_irqs[i] == NO_IRQ) {
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pr_warning("FPGA PIC: can't get irq%d.\n", i);
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continue;
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}
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irq_set_chained_handler(socrates_fpga_irqs[i],
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socrates_fpga_pic_cascade);
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}
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socrates_fpga_pic_iobase = of_iomap(pic, 0);
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raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(0),
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SOCRATES_FPGA_IRQ_MASK << 16);
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(1),
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SOCRATES_FPGA_IRQ_MASK << 16);
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socrates_fpga_pic_write(FPGA_PIC_IRQMASK(2),
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SOCRATES_FPGA_IRQ_MASK << 16);
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raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
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pr_info("FPGA PIC: Setting up Socrates FPGA PIC\n");
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}
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