Taimur Hassan a47cc3ab05 drm/amd/display: Raise DPG height during timing synchronization ...

[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.

[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.

Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2020-10-26 13:29:21 -04:00

..

drm

drm/amd/display: Raise DPG height during timing synchronization

2020-10-26 13:29:21 -04:00

host1x

gpu: host1x: debug: Dump push buffer state

2020-07-17 16:06:14 +02:00

ipu-v3

treewide: Use fallthrough pseudo-keyword

2020-08-23 17:36:59 -05:00

trace

…

vga

vgaarb: mark vga_tryget static

2020-08-01 11:28:17 +02:00

Makefile

…