forked from Minki/linux
533c165fa8
Signed-off-by: John Soni Jose <sony.john-n@emulex.com> Signed-off-by: Jayamohan Kallickal <jayamohan.kallickal@emulex.com> Reviewed-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
1217 lines
31 KiB
C
1217 lines
31 KiB
C
/**
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* Copyright (C) 2005 - 2013 Emulex
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@emulex.com
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*
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* Emulex
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* 3333 Susan Street
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* Costa Mesa, CA 92626
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*/
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#include <scsi/iscsi_proto.h>
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#include "be.h"
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#include "be_mgmt.h"
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#include "be_main.h"
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int beiscsi_pci_soft_reset(struct beiscsi_hba *phba)
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{
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u32 sreset;
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u8 *pci_reset_offset = 0;
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u8 *pci_online0_offset = 0;
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u8 *pci_online1_offset = 0;
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u32 pconline0 = 0;
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u32 pconline1 = 0;
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u32 i;
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pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET;
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pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0;
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pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1;
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sreset = readl((void *)pci_reset_offset);
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sreset |= BE2_SET_RESET;
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writel(sreset, (void *)pci_reset_offset);
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i = 0;
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while (sreset & BE2_SET_RESET) {
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if (i > 64)
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break;
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msleep(100);
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sreset = readl((void *)pci_reset_offset);
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i++;
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}
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if (sreset & BE2_SET_RESET) {
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printk(KERN_ERR DRV_NAME
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" Soft Reset did not deassert\n");
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return -EIO;
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}
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pconline1 = BE2_MPU_IRAM_ONLINE;
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writel(pconline0, (void *)pci_online0_offset);
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writel(pconline1, (void *)pci_online1_offset);
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sreset |= BE2_SET_RESET;
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writel(sreset, (void *)pci_reset_offset);
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i = 0;
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while (sreset & BE2_SET_RESET) {
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if (i > 64)
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break;
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msleep(1);
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sreset = readl((void *)pci_reset_offset);
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i++;
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}
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if (sreset & BE2_SET_RESET) {
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printk(KERN_ERR DRV_NAME
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" MPU Online Soft Reset did not deassert\n");
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return -EIO;
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}
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return 0;
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}
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int be_chk_reset_complete(struct beiscsi_hba *phba)
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{
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unsigned int num_loop;
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u8 *mpu_sem = 0;
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u32 status;
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num_loop = 1000;
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mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
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msleep(5000);
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while (num_loop) {
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status = readl((void *)mpu_sem);
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if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
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break;
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msleep(60);
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num_loop--;
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}
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if ((status & 0x80000000) || (!num_loop)) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : Failed in be_chk_reset_complete"
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"status = 0x%x\n", status);
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return -EIO;
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}
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return 0;
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}
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void be_mcc_notify(struct beiscsi_hba *phba)
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{
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struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
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u32 val = 0;
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val |= mccq->id & DB_MCCQ_RING_ID_MASK;
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val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
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iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
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}
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unsigned int alloc_mcc_tag(struct beiscsi_hba *phba)
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{
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unsigned int tag = 0;
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if (phba->ctrl.mcc_tag_available) {
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tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
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phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
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phba->ctrl.mcc_numtag[tag] = 0;
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}
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if (tag) {
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phba->ctrl.mcc_tag_available--;
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if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
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phba->ctrl.mcc_alloc_index = 0;
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else
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phba->ctrl.mcc_alloc_index++;
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}
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return tag;
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}
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/*
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* beiscsi_mccq_compl()- Wait for completion of MBX
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* @phba: Driver private structure
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* @tag: Tag for the MBX Command
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* @wrb: the WRB used for the MBX Command
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* @cmd_hdr: IOCTL Hdr for the MBX Cmd
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*
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* Waits for MBX completion with the passed TAG.
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*
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* return
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* Success: 0
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* Failure: Non-Zero
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**/
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int beiscsi_mccq_compl(struct beiscsi_hba *phba,
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uint32_t tag, struct be_mcc_wrb **wrb,
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void *cmd_hdr)
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{
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int rc = 0;
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uint32_t mcc_tag_response;
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uint16_t status = 0, addl_status = 0, wrb_num = 0;
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struct be_mcc_wrb *temp_wrb;
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struct be_cmd_req_hdr *ioctl_hdr;
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struct be_cmd_resp_hdr *ioctl_resp_hdr;
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struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
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if (beiscsi_error(phba))
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return -EIO;
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/* wait for the mccq completion */
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rc = wait_event_interruptible_timeout(
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phba->ctrl.mcc_wait[tag],
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phba->ctrl.mcc_numtag[tag],
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msecs_to_jiffies(
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BEISCSI_HOST_MBX_TIMEOUT));
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if (rc <= 0) {
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
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BEISCSI_LOG_CONFIG,
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"BC_%d : MBX Cmd Completion timed out\n");
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rc = -EAGAIN;
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goto release_mcc_tag;
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} else
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rc = 0;
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mcc_tag_response = phba->ctrl.mcc_numtag[tag];
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status = (mcc_tag_response & CQE_STATUS_MASK);
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addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >>
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CQE_STATUS_ADDL_SHIFT);
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if (cmd_hdr) {
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ioctl_hdr = (struct be_cmd_req_hdr *)cmd_hdr;
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} else {
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wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >>
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CQE_STATUS_WRB_SHIFT;
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temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
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ioctl_hdr = embedded_payload(temp_wrb);
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if (wrb)
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*wrb = temp_wrb;
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}
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if (status || addl_status) {
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
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BEISCSI_LOG_CONFIG,
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"BC_%d : MBX Cmd Failed for "
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"Subsys : %d Opcode : %d with "
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"Status : %d and Extd_Status : %d\n",
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ioctl_hdr->subsystem,
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ioctl_hdr->opcode,
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status, addl_status);
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if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
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ioctl_resp_hdr = (struct be_cmd_resp_hdr *) ioctl_hdr;
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if (ioctl_resp_hdr->response_length)
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goto release_mcc_tag;
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}
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rc = -EAGAIN;
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}
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release_mcc_tag:
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/* Release the MCC entry */
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free_mcc_tag(&phba->ctrl, tag);
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return rc;
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}
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void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)
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{
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spin_lock(&ctrl->mbox_lock);
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tag = tag & 0x000000FF;
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ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
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if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
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ctrl->mcc_free_index = 0;
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else
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ctrl->mcc_free_index++;
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ctrl->mcc_tag_available++;
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spin_unlock(&ctrl->mbox_lock);
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}
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bool is_link_state_evt(u32 trailer)
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{
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return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
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ASYNC_TRAILER_EVENT_CODE_MASK) ==
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ASYNC_EVENT_CODE_LINK_STATE);
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}
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static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
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{
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if (compl->flags != 0) {
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compl->flags = le32_to_cpu(compl->flags);
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WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
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return true;
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} else
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return false;
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}
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static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
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{
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compl->flags = 0;
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}
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/*
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* be_mcc_compl_process()- Check the MBX comapletion status
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* @ctrl: Function specific MBX data structure
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* @compl: Completion status of MBX Command
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*
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* Check for the MBX completion status when BMBX method used
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*
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* return
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* Success: Zero
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* Failure: Non-Zero
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**/
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static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl)
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{
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u16 compl_status, extd_status;
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
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struct be_cmd_resp_hdr *resp_hdr;
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be_dws_le_to_cpu(compl, 4);
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compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
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CQE_STATUS_COMPL_MASK;
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if (compl_status != MCC_STATUS_SUCCESS) {
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extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
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CQE_STATUS_EXTD_MASK;
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
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"BC_%d : error in cmd completion: "
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"Subsystem : %d Opcode : %d "
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"status(compl/extd)=%d/%d\n",
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hdr->subsystem, hdr->opcode,
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compl_status, extd_status);
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if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) {
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resp_hdr = (struct be_cmd_resp_hdr *) hdr;
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if (resp_hdr->response_length)
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return 0;
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}
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return -EBUSY;
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}
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return 0;
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}
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int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl)
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{
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u16 compl_status, extd_status;
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unsigned short tag;
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be_dws_le_to_cpu(compl, 4);
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compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
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CQE_STATUS_COMPL_MASK;
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/* The ctrl.mcc_numtag[tag] is filled with
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* [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
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* [7:0] = compl_status
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*/
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tag = (compl->tag0 & 0x000000FF);
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extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
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CQE_STATUS_EXTD_MASK;
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ctrl->mcc_numtag[tag] = 0x80000000;
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ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);
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ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;
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ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);
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wake_up_interruptible(&ctrl->mcc_wait[tag]);
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return 0;
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}
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static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
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{
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struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
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struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
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if (be_mcc_compl_is_new(compl)) {
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queue_tail_inc(mcc_cq);
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return compl;
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}
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return NULL;
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}
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static void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
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{
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iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
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}
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void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
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struct be_async_event_link_state *evt)
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{
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if ((evt->port_link_status == ASYNC_EVENT_LINK_DOWN) ||
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((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
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(evt->port_fault != BEISCSI_PHY_LINK_FAULT_NONE))) {
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phba->state = BE_ADAPTER_LINK_DOWN;
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
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"BC_%d : Link Down on Port %d\n",
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evt->physical_port);
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iscsi_host_for_each_session(phba->shost,
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be2iscsi_fail_session);
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} else if ((evt->port_link_status & ASYNC_EVENT_LINK_UP) ||
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((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
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(evt->port_fault == BEISCSI_PHY_LINK_FAULT_NONE))) {
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phba->state = BE_ADAPTER_UP;
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
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"BC_%d : Link UP on Port %d\n",
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evt->physical_port);
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}
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}
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static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm,
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u16 num_popped)
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{
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u32 val = 0;
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val |= qid & DB_CQ_RING_ID_MASK;
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if (arm)
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val |= 1 << DB_CQ_REARM_SHIFT;
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val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
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iowrite32(val, phba->db_va + DB_CQ_OFFSET);
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}
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int beiscsi_process_mcc(struct beiscsi_hba *phba)
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{
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struct be_mcc_compl *compl;
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int num = 0, status = 0;
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struct be_ctrl_info *ctrl = &phba->ctrl;
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spin_lock_bh(&phba->ctrl.mcc_cq_lock);
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while ((compl = be_mcc_compl_get(phba))) {
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if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
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/* Interpret flags as an async trailer */
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if (is_link_state_evt(compl->flags))
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/* Interpret compl as a async link evt */
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beiscsi_async_link_state_process(phba,
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(struct be_async_event_link_state *) compl);
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else
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_CONFIG |
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BEISCSI_LOG_MBOX,
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"BC_%d : Unsupported Async Event, flags"
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" = 0x%08x\n", compl->flags);
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} else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
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status = be_mcc_compl_process(ctrl, compl);
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atomic_dec(&phba->ctrl.mcc_obj.q.used);
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}
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be_mcc_compl_use(compl);
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num++;
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}
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if (num)
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beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num);
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spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
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return status;
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}
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/*
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* be_mcc_wait_compl()- Wait for MBX completion
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* @phba: driver private structure
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*
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* Wait till no more pending mcc requests are present
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*
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* return
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* Success: 0
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* Failure: Non-Zero
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*
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**/
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static int be_mcc_wait_compl(struct beiscsi_hba *phba)
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{
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int i, status;
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for (i = 0; i < mcc_timeout; i++) {
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if (beiscsi_error(phba))
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return -EIO;
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status = beiscsi_process_mcc(phba);
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if (status)
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return status;
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if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
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break;
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udelay(100);
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}
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if (i == mcc_timeout) {
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
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"BC_%d : FW Timed Out\n");
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phba->fw_timeout = true;
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beiscsi_ue_detect(phba);
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return -EBUSY;
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}
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return 0;
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}
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|
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/*
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* be_mcc_notify_wait()- Notify and wait for Compl
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* @phba: driver private structure
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*
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* Notify MCC requests and wait for completion
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*
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* return
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* Success: 0
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* Failure: Non-Zero
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**/
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int be_mcc_notify_wait(struct beiscsi_hba *phba)
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{
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be_mcc_notify(phba);
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return be_mcc_wait_compl(phba);
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}
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/*
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* be_mbox_db_ready_wait()- Check ready status
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* @ctrl: Function specific MBX data structure
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*
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|
* Check for the ready status of FW to send BMBX
|
|
* commands to adapter.
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero
|
|
**/
|
|
static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
|
|
{
|
|
void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
uint32_t wait = 0;
|
|
u32 ready;
|
|
|
|
do {
|
|
|
|
if (beiscsi_error(phba))
|
|
return -EIO;
|
|
|
|
ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
|
|
if (ready)
|
|
break;
|
|
|
|
if (wait > BEISCSI_HOST_MBX_TIMEOUT) {
|
|
beiscsi_log(phba, KERN_ERR,
|
|
BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
|
|
"BC_%d : FW Timed Out\n");
|
|
phba->fw_timeout = true;
|
|
beiscsi_ue_detect(phba);
|
|
return -EBUSY;
|
|
}
|
|
|
|
mdelay(1);
|
|
wait++;
|
|
} while (true);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* be_mbox_notify: Notify adapter of new BMBX command
|
|
* @ctrl: Function specific MBX data structure
|
|
*
|
|
* Ring doorbell to inform adapter of a BMBX command
|
|
* to process
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero
|
|
**/
|
|
int be_mbox_notify(struct be_ctrl_info *ctrl)
|
|
{
|
|
int status;
|
|
u32 val = 0;
|
|
void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
|
|
struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
|
|
struct be_mcc_mailbox *mbox = mbox_mem->va;
|
|
struct be_mcc_compl *compl = &mbox->compl;
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
|
|
status = be_mbox_db_ready_wait(ctrl);
|
|
if (status)
|
|
return status;
|
|
|
|
val &= ~MPU_MAILBOX_DB_RDY_MASK;
|
|
val |= MPU_MAILBOX_DB_HI_MASK;
|
|
val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
|
|
iowrite32(val, db);
|
|
|
|
status = be_mbox_db_ready_wait(ctrl);
|
|
if (status)
|
|
return status;
|
|
|
|
val = 0;
|
|
val &= ~MPU_MAILBOX_DB_RDY_MASK;
|
|
val &= ~MPU_MAILBOX_DB_HI_MASK;
|
|
val |= (u32) (mbox_mem->dma >> 4) << 2;
|
|
iowrite32(val, db);
|
|
|
|
status = be_mbox_db_ready_wait(ctrl);
|
|
if (status)
|
|
return status;
|
|
|
|
if (be_mcc_compl_is_new(compl)) {
|
|
status = be_mcc_compl_process(ctrl, &mbox->compl);
|
|
be_mcc_compl_use(compl);
|
|
if (status) {
|
|
beiscsi_log(phba, KERN_ERR,
|
|
BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
|
|
"BC_%d : After be_mcc_compl_process\n");
|
|
|
|
return status;
|
|
}
|
|
} else {
|
|
beiscsi_log(phba, KERN_ERR,
|
|
BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
|
|
"BC_%d : Invalid Mailbox Completion\n");
|
|
|
|
return -EBUSY;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Insert the mailbox address into the doorbell in two steps
|
|
* Polls on the mbox doorbell till a command completion (or a timeout) occurs
|
|
*/
|
|
static int be_mbox_notify_wait(struct beiscsi_hba *phba)
|
|
{
|
|
int status;
|
|
u32 val = 0;
|
|
void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
|
|
struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
|
|
struct be_mcc_mailbox *mbox = mbox_mem->va;
|
|
struct be_mcc_compl *compl = &mbox->compl;
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
|
|
status = be_mbox_db_ready_wait(ctrl);
|
|
if (status)
|
|
return status;
|
|
|
|
val |= MPU_MAILBOX_DB_HI_MASK;
|
|
/* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
|
|
val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
|
|
iowrite32(val, db);
|
|
|
|
/* wait for ready to be set */
|
|
status = be_mbox_db_ready_wait(ctrl);
|
|
if (status != 0)
|
|
return status;
|
|
|
|
val = 0;
|
|
/* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
|
|
val |= (u32)(mbox_mem->dma >> 4) << 2;
|
|
iowrite32(val, db);
|
|
|
|
status = be_mbox_db_ready_wait(ctrl);
|
|
if (status != 0)
|
|
return status;
|
|
|
|
/* A cq entry has been made now */
|
|
if (be_mcc_compl_is_new(compl)) {
|
|
status = be_mcc_compl_process(ctrl, &mbox->compl);
|
|
be_mcc_compl_use(compl);
|
|
if (status)
|
|
return status;
|
|
} else {
|
|
beiscsi_log(phba, KERN_ERR,
|
|
BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
|
|
"BC_%d : invalid mailbox completion\n");
|
|
|
|
return -EBUSY;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
|
|
bool embedded, u8 sge_cnt)
|
|
{
|
|
if (embedded)
|
|
wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
|
|
else
|
|
wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
|
|
MCC_WRB_SGE_CNT_SHIFT;
|
|
wrb->payload_length = payload_len;
|
|
be_dws_cpu_to_le(wrb, 8);
|
|
}
|
|
|
|
void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
|
|
u8 subsystem, u8 opcode, int cmd_len)
|
|
{
|
|
req_hdr->opcode = opcode;
|
|
req_hdr->subsystem = subsystem;
|
|
req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
|
|
req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
|
|
}
|
|
|
|
static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
|
|
struct be_dma_mem *mem)
|
|
{
|
|
int i, buf_pages;
|
|
u64 dma = (u64) mem->dma;
|
|
|
|
buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
|
|
for (i = 0; i < buf_pages; i++) {
|
|
pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
|
|
pages[i].hi = cpu_to_le32(upper_32_bits(dma));
|
|
dma += PAGE_SIZE_4K;
|
|
}
|
|
}
|
|
|
|
static u32 eq_delay_to_mult(u32 usec_delay)
|
|
{
|
|
#define MAX_INTR_RATE 651042
|
|
const u32 round = 10;
|
|
u32 multiplier;
|
|
|
|
if (usec_delay == 0)
|
|
multiplier = 0;
|
|
else {
|
|
u32 interrupt_rate = 1000000 / usec_delay;
|
|
if (interrupt_rate == 0)
|
|
multiplier = 1023;
|
|
else {
|
|
multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
|
|
multiplier /= interrupt_rate;
|
|
multiplier = (multiplier + round / 2) / round;
|
|
multiplier = min(multiplier, (u32) 1023);
|
|
}
|
|
}
|
|
return multiplier;
|
|
}
|
|
|
|
struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
|
|
{
|
|
return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
|
|
}
|
|
|
|
struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
|
|
{
|
|
struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
|
|
struct be_mcc_wrb *wrb;
|
|
|
|
BUG_ON(atomic_read(&mccq->used) >= mccq->len);
|
|
wrb = queue_head_node(mccq);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
wrb->tag0 = (mccq->head & 0x000000FF) << 16;
|
|
queue_head_inc(mccq);
|
|
atomic_inc(&mccq->used);
|
|
return wrb;
|
|
}
|
|
|
|
|
|
int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *eq, int eq_delay)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_eq_create *req = embedded_payload(wrb);
|
|
struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &eq->dma_mem;
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_EQ_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
|
|
|
|
AMAP_SET_BITS(struct amap_eq_context, func, req->context,
|
|
PCI_FUNC(ctrl->pdev->devfn));
|
|
AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
|
|
AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
|
|
AMAP_SET_BITS(struct amap_eq_context, count, req->context,
|
|
__ilog2_u32(eq->len / 256));
|
|
AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
|
|
eq_delay_to_mult(eq_delay));
|
|
be_dws_cpu_to_le(req->context, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
eq->id = le16_to_cpu(resp->eq_id);
|
|
eq->created = true;
|
|
}
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* be_cmd_fw_initialize()- Initialize FW
|
|
* @ctrl: Pointer to function control structure
|
|
*
|
|
* Send FW initialize pattern for the function.
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero value
|
|
**/
|
|
int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
int status;
|
|
u8 *endian_check;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
endian_check = (u8 *) wrb;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0x12;
|
|
*endian_check++ = 0x34;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0x56;
|
|
*endian_check++ = 0x78;
|
|
*endian_check++ = 0xFF;
|
|
be_dws_cpu_to_le(wrb, sizeof(*wrb));
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (status)
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BC_%d : be_cmd_fw_initialize Failed\n");
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* be_cmd_fw_uninit()- Uinitialize FW
|
|
* @ctrl: Pointer to function control structure
|
|
*
|
|
* Send FW uninitialize pattern for the function
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero value
|
|
**/
|
|
int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
int status;
|
|
u8 *endian_check;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
endian_check = (u8 *) wrb;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xAA;
|
|
*endian_check++ = 0xBB;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xCC;
|
|
*endian_check++ = 0xDD;
|
|
*endian_check = 0xFF;
|
|
|
|
be_dws_cpu_to_le(wrb, sizeof(*wrb));
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (status)
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BC_%d : be_cmd_fw_uninit Failed\n");
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *cq, struct be_queue_info *eq,
|
|
bool sol_evts, bool no_delay, int coalesce_wm)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_cq_create *req = embedded_payload(wrb);
|
|
struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
struct be_dma_mem *q_mem = &cq->dma_mem;
|
|
void *ctxt = &req->context;
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_CQ_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
|
|
if (is_chip_be2_be3r(phba)) {
|
|
AMAP_SET_BITS(struct amap_cq_context, coalescwm,
|
|
ctxt, coalesce_wm);
|
|
AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
|
|
AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
|
|
__ilog2_u32(cq->len / 256));
|
|
AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
|
|
AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
|
|
AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
|
|
PCI_FUNC(ctrl->pdev->devfn));
|
|
} else {
|
|
req->hdr.version = MBX_CMD_VER2;
|
|
req->page_size = 1;
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
|
|
ctxt, coalesce_wm);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
|
|
ctxt, no_delay);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
|
|
__ilog2_u32(cq->len / 256));
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
|
|
}
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
cq->id = le16_to_cpu(resp->cq_id);
|
|
cq->created = true;
|
|
} else
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BC_%d : In be_cmd_cq_create, status=ox%08x\n",
|
|
status);
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
static u32 be_encoded_q_len(int q_len)
|
|
{
|
|
u32 len_encoded = fls(q_len); /* log2(len) + 1 */
|
|
if (len_encoded == 16)
|
|
len_encoded = 0;
|
|
return len_encoded;
|
|
}
|
|
|
|
int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
|
|
struct be_queue_info *mccq,
|
|
struct be_queue_info *cq)
|
|
{
|
|
struct be_mcc_wrb *wrb;
|
|
struct be_cmd_req_mcc_create *req;
|
|
struct be_dma_mem *q_mem = &mccq->dma_mem;
|
|
struct be_ctrl_info *ctrl;
|
|
void *ctxt;
|
|
int status;
|
|
|
|
spin_lock(&phba->ctrl.mbox_lock);
|
|
ctrl = &phba->ctrl;
|
|
wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
req = embedded_payload(wrb);
|
|
ctxt = &req->context;
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_MCC_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
|
|
AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
|
|
PCI_FUNC(phba->pcidev->devfn));
|
|
AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
|
|
be_encoded_q_len(mccq->len));
|
|
AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify_wait(phba);
|
|
if (!status) {
|
|
struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
|
|
mccq->id = le16_to_cpu(resp->id);
|
|
mccq->created = true;
|
|
}
|
|
spin_unlock(&phba->ctrl.mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
|
|
int queue_type)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
u8 subsys = 0, opcode = 0;
|
|
int status;
|
|
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BC_%d : In beiscsi_cmd_q_destroy "
|
|
"queue_type : %d\n", queue_type);
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
switch (queue_type) {
|
|
case QTYPE_EQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_EQ_DESTROY;
|
|
break;
|
|
case QTYPE_CQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_CQ_DESTROY;
|
|
break;
|
|
case QTYPE_MCCQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_MCC_DESTROY;
|
|
break;
|
|
case QTYPE_WRBQ:
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
|
opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
|
|
break;
|
|
case QTYPE_DPDUQ:
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
|
opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
|
|
break;
|
|
case QTYPE_SGL:
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
|
opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
|
|
break;
|
|
default:
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
BUG();
|
|
return -ENXIO;
|
|
}
|
|
be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
|
|
if (queue_type != QTYPE_SGL)
|
|
req->id = cpu_to_le16(q->id);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *cq,
|
|
struct be_queue_info *dq, int length,
|
|
int entry_size)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_defq_create_req *req = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &dq->dma_mem;
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
void *ctxt = &req->context;
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
|
|
if (is_chip_be2_be3r(phba)) {
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
rx_pdid, ctxt, 0);
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
rx_pdid_valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
ring_size, ctxt,
|
|
be_encoded_q_len(length /
|
|
sizeof(struct phys_addr)));
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
default_buffer_size, ctxt, entry_size);
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
cq_id_recv, ctxt, cq->id);
|
|
} else {
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
rx_pdid, ctxt, 0);
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
rx_pdid_valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
ring_size, ctxt,
|
|
be_encoded_q_len(length /
|
|
sizeof(struct phys_addr)));
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
default_buffer_size, ctxt, entry_size);
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
cq_id_recv, ctxt, cq->id);
|
|
}
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
struct be_defq_create_resp *resp = embedded_payload(wrb);
|
|
|
|
dq->id = le16_to_cpu(resp->id);
|
|
dq->created = true;
|
|
}
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
|
|
struct be_queue_info *wrbq)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_wrbq_create_req *req = embedded_payload(wrb);
|
|
struct be_wrbq_create_resp *resp = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
wrbq->id = le16_to_cpu(resp->cid);
|
|
wrbq->created = true;
|
|
}
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
|
|
struct be_dma_mem *q_mem,
|
|
u32 page_offset, u32 num_pages)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_post_sgl_pages_req *req = embedded_payload(wrb);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
int status;
|
|
unsigned int curr_pages;
|
|
u32 internal_page_offset = 0;
|
|
u32 temp_num_pages = num_pages;
|
|
|
|
if (num_pages == 0xff)
|
|
num_pages = 1;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
do {
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
|
|
sizeof(*req));
|
|
curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
|
|
pages);
|
|
req->num_pages = min(num_pages, curr_pages);
|
|
req->page_offset = page_offset;
|
|
be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
|
|
q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
|
|
internal_page_offset += req->num_pages;
|
|
page_offset += req->num_pages;
|
|
num_pages -= req->num_pages;
|
|
|
|
if (temp_num_pages == 0xff)
|
|
req->num_pages = temp_num_pages;
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (status) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BC_%d : FW CMD to map iscsi frags failed.\n");
|
|
|
|
goto error;
|
|
}
|
|
} while (num_pages > 0);
|
|
error:
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
if (status != 0)
|
|
beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
|
|
return status;
|
|
}
|
|
|
|
int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
|
|
{
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_post_sgl_pages_req *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
|
|
req = embedded_payload(wrb);
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
|
|
status = be_mbox_notify_wait(phba);
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* be_cmd_set_vlan()- Configure VLAN paramters on the adapter
|
|
* @phba: device priv structure instance
|
|
* @vlan_tag: TAG to be set
|
|
*
|
|
* Set the VLAN_TAG for the adapter or Disable VLAN on adapter
|
|
*
|
|
* returns
|
|
* TAG for the MBX Cmd
|
|
* **/
|
|
int be_cmd_set_vlan(struct beiscsi_hba *phba,
|
|
uint16_t vlan_tag)
|
|
{
|
|
unsigned int tag = 0;
|
|
struct be_mcc_wrb *wrb;
|
|
struct be_cmd_set_vlan_req *req;
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
tag = alloc_mcc_tag(phba);
|
|
if (!tag) {
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return tag;
|
|
}
|
|
|
|
wrb = wrb_from_mccq(phba);
|
|
req = embedded_payload(wrb);
|
|
wrb->tag0 |= tag;
|
|
be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
|
|
sizeof(*req));
|
|
|
|
req->interface_hndl = phba->interface_handle;
|
|
req->vlan_priority = vlan_tag;
|
|
|
|
be_mcc_notify(phba);
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return tag;
|
|
}
|