forked from Minki/linux
f079f6d999
Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL found on 8x96. These are picked up from the downstream driver. The PHY part is similar to the other DSI PHYs. The PLL driver requires some trickery so that one DSI PLL can drive both the DSIs (i.e, dual DSI mode). In the case of dual DSI mode. One DSI instance becomes the clock master, and other the clock slave. The master PLL's output (Byte and Pixel clock) is fed to both the DSI hosts/PHYs. When the DSIs are configured in dual DSI mode, the PHY driver communicates to the PLL driver using msm_dsi_pll_set_usecase() which instance is the master and which one is the slave. When setting rate, the master PLL also configures some of the slave PLL/PHY registers which need to be identical to the master's for correct dual DSI behaviour. There are 2 PLL post dividers that should have ideally been modelled as generic clk_divider clocks, but require some customization for dual DSI. In particular, when the master PLL's post-diviers are set, the slave PLL's post-dividers need to be set too. The clk_ops for these use clk_divider's helper ops and flags internally to prevent redundant code. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DSI_PHY_H__
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#define __DSI_PHY_H__
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#include <linux/regulator/consumer.h>
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#include "dsi.h"
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#define dsi_phy_read(offset) msm_readl((offset))
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#define dsi_phy_write(offset, data) msm_writel((data), (offset))
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struct msm_dsi_phy_ops {
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int (*init) (struct msm_dsi_phy *phy);
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int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
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struct msm_dsi_phy_clk_request *clk_req);
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void (*disable)(struct msm_dsi_phy *phy);
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};
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struct msm_dsi_phy_cfg {
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enum msm_dsi_phy_type type;
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struct dsi_reg_config reg_cfg;
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struct msm_dsi_phy_ops ops;
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/*
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* Each cell {phy_id, pll_id} of the truth table indicates
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* if the source PLL selection bit should be set for each PHY.
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* Fill default H/W values in illegal cells, eg. cell {0, 1}.
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*/
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bool src_pll_truthtable[DSI_MAX][DSI_MAX];
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const resource_size_t io_start[DSI_MAX];
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const int num_dsi_phy;
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};
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_pre;
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u32 clk_post;
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u32 clk_zero;
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u32 clk_trail;
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u32 clk_prepare;
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u32 hs_exit;
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u32 hs_zero;
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u32 hs_prepare;
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u32 hs_trail;
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u32 hs_rqst;
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u32 ta_go;
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u32 ta_sure;
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u32 ta_get;
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struct msm_dsi_phy_shared_timings shared_timings;
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/* For PHY v2 only */
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u32 hs_rqst_ckln;
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u32 hs_prep_dly;
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u32 hs_prep_dly_ckln;
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u8 hs_halfbyte_en;
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u8 hs_halfbyte_en_ckln;
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};
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struct msm_dsi_phy {
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struct platform_device *pdev;
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void __iomem *base;
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void __iomem *reg_base;
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void __iomem *lane_base;
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int id;
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struct clk *ahb_clk;
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struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
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struct msm_dsi_dphy_timing timing;
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const struct msm_dsi_phy_cfg *cfg;
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enum msm_dsi_phy_usecase usecase;
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bool regulator_ldo_mode;
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struct msm_dsi_pll *pll;
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};
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/*
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* PHY internal functions
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*/
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int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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u32 bit_mask);
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int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
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#endif /* __DSI_PHY_H__ */
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