ce48b21007
This patch extends the floating point save and restore code to use the VSX load/stores when VSX is available. This will make FP context save/restore marginally slower on FP only code, when VSX is available, as it has to load/store 128bits rather than just 64bits. Mixing FP, VMX and VSX code will get constant architected state. The signals interface is extended to enable access to VSR 0-31 doubleword 1 after discussions with tool chain maintainers. Backward compatibility is maintained. The ptrace interface is also extended to allow access to VSR 0-31 full registers. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
182 lines
4.6 KiB
ArmAsm
182 lines
4.6 KiB
ArmAsm
/*
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* FPU support code, moved here from head.S so that it can be used
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* by chips which use other head-whatever.S files.
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Copyright (C) 1996 Paul Mackerras.
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* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_VSX
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#define REST_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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#define SAVE_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS(n,base); \
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b 3f; \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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#endif
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Load up this task's FP registers from its thread_struct,
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* enable the FPU for the current task and return to the task.
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*/
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_GLOBAL(load_up_fpu)
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mfmsr r5
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ori r5,r5,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC
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MTMSRD(r5) /* enable use of fpu now */
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isync
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/*
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* For SMP, we don't do lazy FPU switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_fpu in switch_to.
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*/
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#ifndef CONFIG_SMP
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LOAD_REG_ADDRBASE(r3, last_task_used_math)
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toreal(r3)
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PPC_LL r4,ADDROFF(last_task_used_math)(r3)
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PPC_LCMPI 0,r4,0
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beq 1f
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toreal(r4)
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addi r4,r4,THREAD /* want last_task_used_math->thread */
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SAVE_32FPVSRS(0, r5, r4)
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mffs fr0
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stfd fr0,THREAD_FPSCR(r4)
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PPC_LL r5,PT_REGS(r4)
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toreal(r5)
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PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r10,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r10 /* disable FP for previous task */
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PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* enable use of FP after return */
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#ifdef CONFIG_PPC32
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mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r9,r9,MSR_FP /* enable FP for current */
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or r9,r9,r4
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#else
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r12,r12,MSR_FP
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or r12,r12,r4
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std r12,_MSR(r1)
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#endif
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lfd fr0,THREAD_FPSCR(r5)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, r4, r5)
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#ifndef CONFIG_SMP
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subi r4,r5,THREAD
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fromreal(r4)
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PPC_STL r4,ADDROFF(last_task_used_math)(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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/* we haven't used ctr or xer or lr */
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blr
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/*
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* giveup_fpu(tsk)
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* Disable FP for the task given as the argument,
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* and save the floating-point registers in its thread_struct.
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* Enables the FPU for use in the kernel on return.
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*/
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_GLOBAL(giveup_fpu)
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mfmsr r5
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ori r5,r5,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC_601
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ISYNC_601
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MTMSRD(r5) /* enable use of fpu now */
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SYNC_601
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isync
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PPC_LCMPI 0,r3,0
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beqlr- /* if no previous owner, done */
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addi r3,r3,THREAD /* want THREAD of task */
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PPC_LL r5,PT_REGS(r3)
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PPC_LCMPI 0,r5,0
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SAVE_32FPVSRS(0, r4 ,r3)
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mffs fr0
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stfd fr0,THREAD_FPSCR(r3)
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beq 1f
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PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r3,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r3 /* disable FP for previous task */
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PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#ifndef CONFIG_SMP
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li r5,0
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LOAD_REG_ADDRBASE(r4,last_task_used_math)
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PPC_STL r5,ADDROFF(last_task_used_math)(r4)
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#endif /* CONFIG_SMP */
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blr
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/*
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* These are used in the alignment trap handler when emulating
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* single-precision loads and stores.
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* We restore and save the fpscr so the task gets the same result
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* and exceptions as if the cpu had performed the load or store.
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*/
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_GLOBAL(cvt_fd)
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lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
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MTFSF_L(0)
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lfs 0,0(r3)
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stfd 0,0(r4)
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mffs 0
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stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */
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blr
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_GLOBAL(cvt_df)
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lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
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MTFSF_L(0)
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lfd 0,0(r3)
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stfs 0,0(r4)
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mffs 0
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stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */
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blr
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