forked from Minki/linux
a1b5b43ffb
The #ifdef logic to clear SCxSR bits using RMW on SCIFA/SCIFB and SCIF
variants with some SCIFA features (sh7705/SH7720/sh7721) has several
drawbacks:
- It wasn't updated for newer R-Mobile variants (APE6),
- It doesn't correctly handle SoCs with both SCIF and SCIFA/B (e.g.
R-Car Gen2, but also legacy sh7723/sh7724),
- It doesn't play well with ARM multi-platform kernels: on R-Car Gen2,
SCIF/SCIFA/SCIFB/HSCIF were handled differently, depending on
whether r8a7740 or sh73a0 support was enabled or not,
Replace the #ifdef logic by runtime logic to fix this.
SCIFA/SCIFB and SCIF on sh7705/sh7720/sh7721 use RMW to clear error
bits, other variants use plain stores, as before.
Note that this changes behavior for SCIFA on sh7723/sh7724 (these SoCs
have both SCIF and SCIFA), which didn't use RMW before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
130 lines
5.1 KiB
C
130 lines
5.1 KiB
C
#include <linux/bitops.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#define SCI_MAJOR 204
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#define SCI_MINOR_START 8
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/*
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* SCI register subset common for all port types.
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* Not all registers will exist on all parts.
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*/
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enum {
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SCSMR, /* Serial Mode Register */
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SCBRR, /* Bit Rate Register */
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SCSCR, /* Serial Control Register */
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SCxSR, /* Serial Status Register */
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SCFCR, /* FIFO Control Register */
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SCFDR, /* FIFO Data Count Register */
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SCxTDR, /* Transmit (FIFO) Data Register */
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SCxRDR, /* Receive (FIFO) Data Register */
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SCLSR, /* Line Status Register */
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SCTFDR, /* Transmit FIFO Data Count Register */
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SCRFDR, /* Receive FIFO Data Count Register */
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SCSPTR, /* Serial Port Register */
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HSSRR, /* Sampling Rate Register */
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SCPCR, /* Serial Port Control Register */
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SCPDR, /* Serial Port Data Register */
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SCIx_NR_REGS,
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};
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/* SCSMR (Serial Mode Register) */
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#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
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#define SCSMR_PE BIT(5) /* Parity Enable */
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#define SCSMR_ODD BIT(4) /* Odd Parity */
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#define SCSMR_STOP BIT(3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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/* Serial Control Register, SCIFA/SCIFB only bits */
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#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
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/* SCxSR (Serial Status Register) on SCI */
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#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
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#define SCI_RDRF BIT(6) /* Receive Data Register Full */
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#define SCI_ORER BIT(5) /* Overrun Error */
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#define SCI_FER BIT(4) /* Framing Error */
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#define SCI_PER BIT(3) /* Parity Error */
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#define SCI_TEND BIT(2) /* Transmit End */
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#define SCI_RESERVED 0x03 /* All reserved bits */
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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#define SCI_RDxF_CLEAR ~(SCI_RESERVED | SCI_RDRF)
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#define SCI_ERROR_CLEAR ~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)
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#define SCI_TDxE_CLEAR ~(SCI_RESERVED | SCI_TEND | SCI_TDRE)
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#define SCI_BREAK_CLEAR ~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)
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/* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
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#define SCIF_ER BIT(7) /* Receive Error */
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#define SCIF_TEND BIT(6) /* Transmission End */
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#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
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#define SCIF_BRK BIT(4) /* Break Detect */
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#define SCIF_FER BIT(3) /* Framing Error */
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#define SCIF_PER BIT(2) /* Parity Error */
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#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
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#define SCIF_DR BIT(0) /* Receive Data Ready */
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/* SCIF only (optional) */
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#define SCIF_PERC 0xf000 /* Number of Parity Errors */
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#define SCIF_FERC 0x0f00 /* Number of Framing Errors */
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/*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
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#define SCIFA_ORER BIT(9) /* Overrun Error */
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
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#define SCIF_RDxF_CLEAR ~(SCIF_DR | SCIF_RDF)
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#define SCIF_ERROR_CLEAR ~(SCIFA_ORER | SCIF_PER | SCIF_FER | SCIF_ER)
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#define SCIF_TDxE_CLEAR ~(SCIF_TDFE)
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#define SCIF_BREAK_CLEAR ~(SCIF_PER | SCIF_FER | SCIF_BRK)
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/* SCFCR (FIFO Control Register) */
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#define SCFCR_MCE BIT(3) /* Modem Control Enable */
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#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
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#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
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#define SCFCR_LOOP BIT(0) /* Loopback Test */
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/* SCLSR (Line Status Register) on (H)SCIF */
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#define SCLSR_ORER BIT(0) /* Overrun Error */
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/* SCSPTR (Serial Port Register), optional */
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#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */
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#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */
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#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */
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#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */
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#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
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#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
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/* HSSRR HSCIF */
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#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
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/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
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#define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */
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#define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */
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/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
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#define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */
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#define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */
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#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
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#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
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#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
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#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
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#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
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#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
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#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
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#define SCxSR_RDxF_CLEAR(port) \
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(((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
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#define SCxSR_ERROR_CLEAR(port) \
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(((port)->type == PORT_SCI) ? SCI_ERROR_CLEAR : SCIF_ERROR_CLEAR)
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#define SCxSR_TDxE_CLEAR(port) \
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(((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
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#define SCxSR_BREAK_CLEAR(port) \
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(((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
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