forked from Minki/linux
392 lines
11 KiB
C
392 lines
11 KiB
C
/*
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* Copyright 2009 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <drm/drmP.h>
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#include <drm/drm_dp_helper.h>
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#include "nouveau_drm.h"
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#include "nouveau_connector.h"
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#include "nouveau_encoder.h"
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#include "nouveau_crtc.h"
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#include <core/class.h>
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#include <subdev/gpio.h>
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#include <subdev/i2c.h>
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/******************************************************************************
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* link training
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*****************************************************************************/
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struct dp_state {
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struct nouveau_i2c_port *auxch;
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struct nouveau_object *core;
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struct dcb_output *dcb;
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int crtc;
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u8 *dpcd;
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int link_nr;
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u32 link_bw;
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u8 stat[6];
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u8 conf[4];
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};
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static void
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dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct dcb_output *dcb = dp->dcb;
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const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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const u32 moff = (dp->crtc << 3) | (link << 2) | or;
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u8 sink[2];
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u32 data;
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NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
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/* set desired link configuration on the source */
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data = ((dp->link_bw / 27000) << 8) | dp->link_nr;
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if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
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data |= NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH;
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nv_call(dp->core, NV94_DISP_SOR_DP_LNKCTL + moff, data);
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/* inform the sink of the new configuration */
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sink[0] = dp->link_bw / 27000;
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sink[1] = dp->link_nr;
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if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
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sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
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}
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static void
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dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct dcb_output *dcb = dp->dcb;
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const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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const u32 moff = (dp->crtc << 3) | (link << 2) | or;
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u8 sink_tp;
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NV_DEBUG(drm, "training pattern %d\n", pattern);
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nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, pattern);
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nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
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sink_tp &= ~DP_TRAINING_PATTERN_MASK;
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sink_tp |= pattern;
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nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
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}
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static int
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dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct dcb_output *dcb = dp->dcb;
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const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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const u32 moff = (dp->crtc << 3) | (link << 2) | or;
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int i;
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for (i = 0; i < dp->link_nr; i++) {
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u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
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u8 lpre = (lane & 0x0c) >> 2;
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u8 lvsw = (lane & 0x03) >> 0;
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dp->conf[i] = (lpre << 3) | lvsw;
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if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
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dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
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if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
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dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
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nv_call(dp->core, NV94_DISP_SOR_DP_DRVCTL(i) + moff, (lvsw << 8) | lpre);
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}
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return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
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}
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static int
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dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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int ret;
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udelay(delay);
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ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
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if (ret)
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return ret;
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NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
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return 0;
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}
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static int
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dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
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{
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bool cr_done = false, abort = false;
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int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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int tries = 0, i;
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dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
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do {
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if (dp_link_train_commit(dev, dp) ||
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dp_link_train_update(dev, dp, 100))
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break;
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cr_done = true;
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for (i = 0; i < dp->link_nr; i++) {
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u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DP_LANE_CR_DONE)) {
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cr_done = false;
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if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
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abort = true;
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break;
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}
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}
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if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
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voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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tries = 0;
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}
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} while (!cr_done && !abort && ++tries < 5);
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return cr_done ? 0 : -1;
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}
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static int
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dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
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{
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bool eq_done, cr_done = true;
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int tries = 0, i;
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dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
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do {
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if (dp_link_train_update(dev, dp, 400))
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break;
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eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
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for (i = 0; i < dp->link_nr && eq_done; i++) {
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u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DP_LANE_CR_DONE))
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cr_done = false;
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if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
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!(lane & DP_LANE_SYMBOL_LOCKED))
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eq_done = false;
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}
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if (dp_link_train_commit(dev, dp))
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break;
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} while (!eq_done && cr_done && ++tries <= 5);
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return eq_done ? 0 : -1;
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}
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static void
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dp_link_train_init(struct drm_device *dev, struct dp_state *dp, bool spread)
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{
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struct dcb_output *dcb = dp->dcb;
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const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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const u32 moff = (dp->crtc << 3) | (link << 2) | or;
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nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, (spread ?
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NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON :
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NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF) |
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NV94_DISP_SOR_DP_TRAIN_OP_INIT);
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}
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static void
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dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
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{
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struct dcb_output *dcb = dp->dcb;
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const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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const u32 moff = (dp->crtc << 3) | (link << 2) | or;
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nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff,
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NV94_DISP_SOR_DP_TRAIN_OP_FINI);
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}
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static bool
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nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
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struct nouveau_object *core)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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struct nouveau_connector *nv_connector =
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nouveau_encoder_connector_get(nv_encoder);
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struct drm_device *dev = encoder->dev;
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
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struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
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const u32 bw_list[] = { 270000, 162000, 0 };
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const u32 *link_bw = bw_list;
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struct dp_state dp;
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dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
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if (!dp.auxch)
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return false;
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dp.core = core;
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dp.dcb = nv_encoder->dcb;
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dp.crtc = nv_crtc->index;
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dp.dpcd = nv_encoder->dp.dpcd;
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/* adjust required bandwidth for 8B/10B coding overhead */
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datarate = (datarate / 8) * 10;
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/* some sinks toggle hotplug in response to some of the actions
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* we take during link training (DP_SET_POWER is one), we need
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* to ignore them for the moment to avoid races.
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*/
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gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);
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/* enable down-spreading and execute pre-train script from vbios */
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dp_link_train_init(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
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/* start off at highest link rate supported by encoder and display */
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while (*link_bw > nv_encoder->dp.link_bw)
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link_bw++;
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while (link_bw[0]) {
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/* find minimum required lane count at this link rate */
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dp.link_nr = nv_encoder->dp.link_nr;
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while ((dp.link_nr >> 1) * link_bw[0] > datarate)
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dp.link_nr >>= 1;
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/* drop link rate to minimum with this lane count */
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while ((link_bw[1] * dp.link_nr) > datarate)
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link_bw++;
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dp.link_bw = link_bw[0];
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/* program selected link configuration */
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dp_set_link_config(dev, &dp);
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/* attempt to train the link at this configuration */
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memset(dp.stat, 0x00, sizeof(dp.stat));
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if (!dp_link_train_cr(dev, &dp) &&
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!dp_link_train_eq(dev, &dp))
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break;
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/* retry at lower rate */
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link_bw++;
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}
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/* finish link training */
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dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
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/* execute post-train script from vbios */
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dp_link_train_fini(dev, &dp);
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/* re-enable hotplug detect */
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gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
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return true;
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}
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void
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nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
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struct nouveau_object *core)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_drm *drm = nouveau_drm(encoder->dev);
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struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
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struct nouveau_i2c_port *auxch;
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u8 status;
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auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
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if (!auxch)
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return;
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if (mode == DRM_MODE_DPMS_ON)
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status = DP_SET_POWER_D0;
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else
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status = DP_SET_POWER_D3;
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nv_wraux(auxch, DP_SET_POWER, &status, 1);
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if (mode == DRM_MODE_DPMS_ON)
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nouveau_dp_link_train(encoder, datarate, core);
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}
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static void
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nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
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u8 *dpcd)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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u8 buf[3];
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if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
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return;
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if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
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NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
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NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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}
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bool
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nouveau_dp_detect(struct drm_encoder *encoder)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
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struct nouveau_i2c_port *auxch;
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u8 *dpcd = nv_encoder->dp.dpcd;
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int ret;
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auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
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if (!auxch)
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return false;
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ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
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if (ret)
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return false;
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nv_encoder->dp.link_bw = 27000 * dpcd[1];
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nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
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NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
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nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
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NV_DEBUG(drm, "encoder: %dx%d\n",
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nv_encoder->dcb->dpconf.link_nr,
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nv_encoder->dcb->dpconf.link_bw);
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if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
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nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
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if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
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nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
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NV_DEBUG(drm, "maximum: %dx%d\n",
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nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
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nouveau_dp_probe_oui(dev, auxch, dpcd);
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return true;
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}
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