forked from Minki/linux
a88afa46b8
When the kernel is configured to use the Thumb-2 instruction set
"suspend-to-memory" fails to resume. Observed on a Colibri iMX6ULL
(i.MX 6ULL) and Apalis iMX6 (i.MX 6Q).
It looks like the CPU resumes unconditionally in ARM instruction mode
and then chokes on the presented Thumb-2 code it should execute.
Fix this by using the arm instruction set for all code in
suspend-imx6.S.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Fixes: df595746fa ("ARM: imx: add suspend in ocram support for i.mx6q")
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
331 lines
7.7 KiB
ArmAsm
331 lines
7.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "hardware.h"
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/*
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* ==================== low level suspend ====================
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*
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* Better to follow below rules to use ARM registers:
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* r0: pm_info structure address;
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* r1 ~ r4: for saving pm_info members;
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* r5 ~ r10: free registers;
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* r11: io base address.
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*
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* suspend ocram space layout:
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* ======================== high address ======================
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* .
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* .
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* .
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* ^
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* ^
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* ^
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* imx6_suspend code
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* PM_INFO structure(imx6_cpu_pm_info)
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* ======================== low address =======================
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*/
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/*
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* Below offsets are based on struct imx6_cpu_pm_info
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* which defined in arch/arm/mach-imx/pm-imx6q.c, this
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* structure contains necessary pm info for low level
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* suspend related code.
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*/
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#define PM_INFO_PBASE_OFFSET 0x0
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#define PM_INFO_RESUME_ADDR_OFFSET 0x4
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#define PM_INFO_DDR_TYPE_OFFSET 0x8
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#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC
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#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
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#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
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#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18
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#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C
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#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20
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#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24
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#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28
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#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C
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#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30
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#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34
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#define PM_INFO_MX6Q_L2_P_OFFSET 0x38
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#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C
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#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40
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#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44
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#define MX6Q_SRC_GPR1 0x20
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#define MX6Q_SRC_GPR2 0x24
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#define MX6Q_MMDC_MAPSR 0x404
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#define MX6Q_MMDC_MPDGCTRL0 0x83c
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#define MX6Q_GPC_IMR1 0x08
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#define MX6Q_GPC_IMR2 0x0c
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#define MX6Q_GPC_IMR3 0x10
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#define MX6Q_GPC_IMR4 0x14
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#define MX6Q_CCM_CCR 0x0
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.align 3
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.arm
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.macro sync_l2_cache
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/* sync L2 cache to drain L2's buffers to DRAM. */
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#ifdef CONFIG_CACHE_L2X0
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ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
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teq r11, #0
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beq 6f
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mov r6, #0x0
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str r6, [r11, #L2X0_CACHE_SYNC]
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1:
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ldr r6, [r11, #L2X0_CACHE_SYNC]
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ands r6, r6, #0x1
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bne 1b
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6:
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#endif
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.endm
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.macro resume_mmdc
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/* restore MMDC IO */
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cmp r5, #0x0
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ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
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ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
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ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
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ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
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add r7, r7, r0
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1:
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ldr r8, [r7], #0x4
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ldr r9, [r7], #0x4
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str r9, [r11, r8]
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subs r6, r6, #0x1
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bne 1b
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cmp r5, #0x0
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ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
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ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
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cmp r3, #IMX_DDR_TYPE_LPDDR2
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bne 4f
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/* reset read FIFO, RST_RD_FIFO */
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ldr r7, =MX6Q_MMDC_MPDGCTRL0
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ldr r6, [r11, r7]
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orr r6, r6, #(1 << 31)
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str r6, [r11, r7]
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2:
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ldr r6, [r11, r7]
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ands r6, r6, #(1 << 31)
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bne 2b
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/* reset FIFO a second time */
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ldr r6, [r11, r7]
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orr r6, r6, #(1 << 31)
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str r6, [r11, r7]
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3:
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ldr r6, [r11, r7]
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ands r6, r6, #(1 << 31)
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bne 3b
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4:
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/* let DDR out of self-refresh */
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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bic r7, r7, #(1 << 21)
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str r7, [r11, #MX6Q_MMDC_MAPSR]
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5:
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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ands r7, r7, #(1 << 25)
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bne 5b
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/* enable DDR auto power saving */
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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bic r7, r7, #0x1
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str r7, [r11, #MX6Q_MMDC_MAPSR]
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.endm
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ENTRY(imx6_suspend)
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ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
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ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
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ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
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ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
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/*
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* counting the resume address in iram
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* to set it in SRC register.
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*/
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ldr r6, =imx6_suspend
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ldr r7, =resume
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sub r7, r7, r6
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add r8, r1, r4
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add r9, r8, r7
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/*
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* make sure TLB contain the addr we want,
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* as we will access them after MMDC IO floated.
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*/
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ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
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ldr r6, [r11, #0x0]
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ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
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ldr r6, [r11, #0x0]
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ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
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ldr r6, [r11, #0x0]
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/* use r11 to store the IO address */
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ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
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/* store physical resume addr and pm_info address. */
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str r9, [r11, #MX6Q_SRC_GPR1]
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str r1, [r11, #MX6Q_SRC_GPR2]
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/* need to sync L2 cache before DSM. */
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sync_l2_cache
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ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
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/*
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* put DDR explicitly into self-refresh and
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* disable automatic power savings.
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*/
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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orr r7, r7, #0x1
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str r7, [r11, #MX6Q_MMDC_MAPSR]
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/* make the DDR explicitly enter self-refresh. */
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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orr r7, r7, #(1 << 21)
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str r7, [r11, #MX6Q_MMDC_MAPSR]
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poll_dvfs_set:
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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ands r7, r7, #(1 << 25)
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beq poll_dvfs_set
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ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
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ldr r6, =0x0
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ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
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ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
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add r8, r8, r0
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/* LPDDR2's last 3 IOs need special setting */
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cmp r3, #IMX_DDR_TYPE_LPDDR2
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subeq r7, r7, #0x3
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set_mmdc_io_lpm:
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ldr r9, [r8], #0x8
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str r6, [r11, r9]
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subs r7, r7, #0x1
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bne set_mmdc_io_lpm
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cmp r3, #IMX_DDR_TYPE_LPDDR2
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bne set_mmdc_io_lpm_done
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ldr r6, =0x1000
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ldr r9, [r8], #0x8
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str r6, [r11, r9]
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ldr r9, [r8], #0x8
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str r6, [r11, r9]
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ldr r6, =0x80000
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ldr r9, [r8]
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str r6, [r11, r9]
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set_mmdc_io_lpm_done:
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/*
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* mask all GPC interrupts before
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* enabling the RBC counters to
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* avoid the counter starting too
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* early if an interupt is already
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* pending.
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*/
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ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
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ldr r6, [r11, #MX6Q_GPC_IMR1]
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ldr r7, [r11, #MX6Q_GPC_IMR2]
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ldr r8, [r11, #MX6Q_GPC_IMR3]
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ldr r9, [r11, #MX6Q_GPC_IMR4]
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ldr r10, =0xffffffff
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str r10, [r11, #MX6Q_GPC_IMR1]
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str r10, [r11, #MX6Q_GPC_IMR2]
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str r10, [r11, #MX6Q_GPC_IMR3]
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str r10, [r11, #MX6Q_GPC_IMR4]
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/*
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* enable the RBC bypass counter here
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* to hold off the interrupts. RBC counter
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* = 32 (1ms), Minimum RBC delay should be
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* 400us for the analog LDOs to power down.
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*/
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ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
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ldr r10, [r11, #MX6Q_CCM_CCR]
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bic r10, r10, #(0x3f << 21)
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orr r10, r10, #(0x20 << 21)
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str r10, [r11, #MX6Q_CCM_CCR]
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/* enable the counter. */
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ldr r10, [r11, #MX6Q_CCM_CCR]
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orr r10, r10, #(0x1 << 27)
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str r10, [r11, #MX6Q_CCM_CCR]
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/* unmask all the GPC interrupts. */
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ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
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str r6, [r11, #MX6Q_GPC_IMR1]
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str r7, [r11, #MX6Q_GPC_IMR2]
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str r8, [r11, #MX6Q_GPC_IMR3]
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str r9, [r11, #MX6Q_GPC_IMR4]
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/*
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* now delay for a short while (3usec)
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* ARM is at 1GHz at this point
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* so a short loop should be enough.
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* this delay is required to ensure that
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* the RBC counter can start counting in
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* case an interrupt is already pending
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* or in case an interrupt arrives just
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* as ARM is about to assert DSM_request.
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*/
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ldr r6, =2000
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rbc_loop:
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subs r6, r6, #0x1
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bne rbc_loop
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/* Zzz, enter stop mode */
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wfi
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nop
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nop
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nop
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nop
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/*
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* run to here means there is pending
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* wakeup source, system should auto
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* resume, we need to restore MMDC IO first
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*/
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mov r5, #0x0
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resume_mmdc
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/* return to suspend finish */
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ret lr
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resume:
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/* invalidate L1 I-cache first */
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mov r6, #0x0
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mcr p15, 0, r6, c7, c5, 0
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mcr p15, 0, r6, c7, c5, 6
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/* enable the Icache and branch prediction */
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mov r6, #0x1800
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mcr p15, 0, r6, c1, c0, 0
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isb
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/* get physical resume address from pm_info. */
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ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
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/* clear core0's entry and parameter */
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ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
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mov r7, #0x0
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str r7, [r11, #MX6Q_SRC_GPR1]
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str r7, [r11, #MX6Q_SRC_GPR2]
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ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
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mov r5, #0x1
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resume_mmdc
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ret lr
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ENDPROC(imx6_suspend)
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