044c0629b5
VCE DPM works similarly to SCLK DPM. Add a similar interface for VCE for forcing the VCE clocks. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
240 lines
6.4 KiB
C
240 lines
6.4 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __CZ_DPM_H__
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#define __CZ_DPM_H__
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#include "smu8_fusion.h"
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#define CZ_AT_DFLT 30
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#define CZ_NUM_NBPSTATES 4
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#define CZ_NUM_NBPMEMORY_CLOCK 2
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#define CZ_MAX_HARDWARE_POWERLEVELS 8
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#define CZ_MAX_DISPLAY_CLOCK_LEVEL 8
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#define CZ_MAX_DISPLAYPHY_IDS 10
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#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
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#define SMC_RAM_END 0x40000
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#define DPMFlags_SCLK_Enabled 0x00000001
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#define DPMFlags_UVD_Enabled 0x00000002
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#define DPMFlags_VCE_Enabled 0x00000004
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#define DPMFlags_ACP_Enabled 0x00000008
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#define DPMFlags_ForceHighestValid 0x40000000
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#define DPMFlags_Debug 0x80000000
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/* Do not change the following, it is also defined in SMU8.h */
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#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001
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#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
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#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000
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#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000
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/* temporary solution to SetMinDeepSleepSclk
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* should indicate by display adaptor
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* 10k Hz unit*/
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#define CZ_MIN_DEEP_SLEEP_SCLK 800
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enum cz_pt_config_reg_type {
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CZ_CONFIGREG_MMR = 0,
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CZ_CONFIGREG_SMC_IND,
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CZ_CONFIGREG_DIDT_IND,
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CZ_CONFIGREG_CACHE,
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CZ_CONFIGREG_MAX
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};
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struct cz_pt_config_reg {
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uint32_t offset;
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uint32_t mask;
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uint32_t shift;
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uint32_t value;
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enum cz_pt_config_reg_type type;
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};
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struct cz_dpm_entry {
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uint32_t soft_min_clk;
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uint32_t hard_min_clk;
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uint32_t soft_max_clk;
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uint32_t hard_max_clk;
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};
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struct cz_pl {
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uint32_t sclk;
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uint8_t vddc_index;
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uint8_t ds_divider_index;
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uint8_t ss_divider_index;
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uint8_t allow_gnb_slow;
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uint8_t force_nbp_state;
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uint8_t display_wm;
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uint8_t vce_wm;
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};
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struct cz_ps {
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struct cz_pl levels[CZ_MAX_HARDWARE_POWERLEVELS];
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uint32_t num_levels;
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bool need_dfs_bypass;
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uint8_t dpm0_pg_nb_ps_lo;
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uint8_t dpm0_pg_nb_ps_hi;
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uint8_t dpmx_nb_ps_lo;
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uint8_t dpmx_nb_ps_hi;
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bool force_high;
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};
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struct cz_displayphy_entry {
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uint8_t phy_present;
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uint8_t active_lane_mapping;
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uint8_t display_conf_type;
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uint8_t num_active_lanes;
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};
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struct cz_displayphy_info {
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bool phy_access_initialized;
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struct cz_displayphy_entry entries[CZ_MAX_DISPLAYPHY_IDS];
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};
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struct cz_sys_info {
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uint32_t bootup_uma_clk;
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uint32_t bootup_sclk;
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uint32_t dentist_vco_freq;
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uint32_t nb_dpm_enable;
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uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK];
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uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
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uint8_t nbp_voltage_index[CZ_NUM_NBPSTATES];
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uint32_t display_clock[CZ_MAX_DISPLAY_CLOCK_LEVEL];
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uint16_t bootup_nb_voltage_index;
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uint8_t htc_tmp_lmt;
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uint8_t htc_hyst_lmt;
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uint32_t uma_channel_number;
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};
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struct cz_power_info {
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uint32_t active_target[CZ_MAX_HARDWARE_POWERLEVELS];
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struct cz_sys_info sys_info;
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struct cz_pl boot_pl;
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bool disable_nb_ps3_in_battery;
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bool battery_state;
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uint32_t lowest_valid;
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uint32_t highest_valid;
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uint16_t high_voltage_threshold;
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/* smc offsets */
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uint32_t sram_end;
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uint32_t dpm_table_start;
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uint32_t soft_regs_start;
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/* dpm SMU tables */
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uint8_t uvd_level_count;
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uint8_t vce_level_count;
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uint8_t acp_level_count;
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uint32_t fps_high_threshold;
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uint32_t fps_low_threshold;
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/* dpm table */
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uint32_t dpm_flags;
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struct cz_dpm_entry sclk_dpm;
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struct cz_dpm_entry uvd_dpm;
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struct cz_dpm_entry vce_dpm;
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struct cz_dpm_entry acp_dpm;
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uint8_t uvd_boot_level;
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uint8_t uvd_interval;
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uint8_t vce_boot_level;
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uint8_t vce_interval;
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uint8_t acp_boot_level;
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uint8_t acp_interval;
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uint8_t graphics_boot_level;
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uint8_t graphics_interval;
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uint8_t graphics_therm_throttle_enable;
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uint8_t graphics_voltage_change_enable;
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uint8_t graphics_clk_slow_enable;
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uint8_t graphics_clk_slow_divider;
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uint32_t low_sclk_interrupt_threshold;
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bool uvd_power_gated;
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bool vce_power_gated;
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bool acp_power_gated;
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uint32_t active_process_mask;
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uint32_t mgcg_cgtt_local0;
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uint32_t mgcg_cgtt_local1;
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uint32_t clock_slow_down_step;
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uint32_t skip_clock_slow_down;
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bool enable_nb_ps_policy;
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uint32_t voting_clients;
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uint32_t voltage_drop_threshold;
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uint32_t gfx_pg_threshold;
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uint32_t max_sclk_level;
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uint32_t max_uvd_level;
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uint32_t max_vce_level;
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/* flags */
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bool didt_enabled;
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bool video_start;
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bool cac_enabled;
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bool bapm_enabled;
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bool nb_dpm_enabled_by_driver;
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bool nb_dpm_enabled;
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bool auto_thermal_throttling_enabled;
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bool dpm_enabled;
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bool need_pptable_upload;
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/* caps */
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bool caps_cac;
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bool caps_power_containment;
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bool caps_sq_ramping;
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bool caps_db_ramping;
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bool caps_td_ramping;
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bool caps_tcp_ramping;
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bool caps_sclk_throttle_low_notification;
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bool caps_fps;
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bool caps_uvd_dpm;
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bool caps_uvd_pg;
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bool caps_vce_dpm;
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bool caps_vce_pg;
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bool caps_acp_dpm;
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bool caps_acp_pg;
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bool caps_stable_power_state;
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bool caps_enable_dfs_bypass;
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bool caps_sclk_ds;
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bool caps_voltage_island;
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/* power state */
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struct amdgpu_ps current_rps;
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struct cz_ps current_ps;
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struct amdgpu_ps requested_rps;
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struct cz_ps requested_ps;
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bool uvd_power_down;
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bool vce_power_down;
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bool acp_power_down;
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bool uvd_dynamic_pg;
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};
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/* cz_smc.c */
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uint32_t cz_get_argument(struct amdgpu_device *adev);
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int cz_send_msg_to_smc(struct amdgpu_device *adev, uint16_t msg);
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int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
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uint16_t msg, uint32_t parameter);
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int cz_read_smc_sram_dword(struct amdgpu_device *adev,
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uint32_t smc_address, uint32_t *value, uint32_t limit);
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int cz_smu_upload_pptable(struct amdgpu_device *adev);
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int cz_smu_download_pptable(struct amdgpu_device *adev, void **table);
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#endif
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