Nicholas Kazlauskas a07f8b9983 drm/amd/display: Send s0i2_rdy in stream_count == 0 optimization ... [Why] Otherwise SMU won't mark Display as idle when trying to perform s2idle. [How] Mark the bit in the dcn31 codepath, doesn't apply to older ASIC. It needed to be split from phy refclk off to prevent entering s2idle when PSR was engaged but driver was not ready. Fixes: 118a331516 ("drm/amd/display: Add DCN3.1 clock manager support") Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-12-28 16:51:24 -05:00
..
drm	drm/amd/display: Send s0i2_rdy in stream_count == 0 optimization	2021-12-28 16:51:24 -05:00
host1x	gpu: host1x: Plug potential memory leak	2021-09-16 18:06:52 +02:00
ipu-v3	media: i.MX6: Support 16-bit BT.1120 video input	2021-10-19 08:08:38 +01:00
trace
vga	vgaarb: don't pass a cookie to vga_client_register	2021-07-21 10:29:10 +02:00
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