400dc0f861
Up to now, linear and IMMR mappings are managed via huge TLB entries through specific code directly in TLB miss handlers. This implies some patching of the TLB miss handlers at startup, and a lot of dedicated code. Remove all this specific dedicated code. For now we are back to normal handling via standard 4k pages. In the next patches, linear memory mapping and IMMR mapping will be managed through huge pages. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/221b7e3ead80a5969629938c023f8cfe45fdd2fb.1589866984.git.christophe.leroy@csgroup.eu |
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| .. | ||
| 8xx.c | ||
| 40x.c | ||
| 44x.c | ||
| book3e_hugetlbpage.c | ||
| book3e_pgtable.c | ||
| fsl_booke.c | ||
| kaslr_booke.c | ||
| Makefile | ||
| mmu_context.c | ||
| tlb_low_64e.S | ||
| tlb_low.S | ||
| tlb.c | ||