forked from Minki/linux
9ede365aa6
The HWMOD data for OMAP2 and 3 are currently not up to date regarding DSS (OMAP4 HWMOD data is fine). This patch makes the DSS driver to get the opt clocks needed for OMAP2/3 with the old clock names, thus allowing DSS driver to use runtime PM. The HWMOD databases should be fixes ASAP, and this patch can be reverted after that. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
537 lines
16 KiB
C
537 lines
16 KiB
C
/*
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* linux/drivers/video/omap2/dss/dss.h
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OMAP2_DSS_H
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#define __OMAP2_DSS_H
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#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
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#define DEBUG
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#endif
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#ifdef DEBUG
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extern unsigned int dss_debug;
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#ifdef DSS_SUBSYS_NAME
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#define DSSDBG(format, ...) \
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if (dss_debug) \
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printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
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## __VA_ARGS__)
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#else
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#define DSSDBG(format, ...) \
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if (dss_debug) \
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printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSDBGF(format, ...) \
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if (dss_debug) \
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printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
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": %s(" format ")\n", \
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__func__, \
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## __VA_ARGS__)
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#else
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#define DSSDBGF(format, ...) \
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if (dss_debug) \
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printk(KERN_DEBUG "omapdss: " \
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": %s(" format ")\n", \
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__func__, \
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## __VA_ARGS__)
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#endif
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#else /* DEBUG */
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#define DSSDBG(format, ...)
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#define DSSDBGF(format, ...)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSERR(format, ...) \
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printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
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## __VA_ARGS__)
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#else
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#define DSSERR(format, ...) \
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printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSINFO(format, ...) \
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printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
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## __VA_ARGS__)
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#else
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#define DSSINFO(format, ...) \
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printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSWARN(format, ...) \
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printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
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## __VA_ARGS__)
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#else
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#define DSSWARN(format, ...) \
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printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
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#endif
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/* OMAP TRM gives bitfields as start:end, where start is the higher bit
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number. For example 7:0 */
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#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
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#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
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#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
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#define FLD_MOD(orig, val, start, end) \
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(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
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enum omap_parallel_interface_mode {
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OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */
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OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */
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OMAP_DSS_PARALLELMODE_DSI,
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};
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enum dss_hdmi_venc_clk_source_select {
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DSS_VENC_TV_CLK = 0,
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DSS_HDMI_M_PCLK = 1,
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};
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struct dss_clock_info {
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/* rates that we get with dividers below */
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unsigned long fck;
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/* dividers */
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u16 fck_div;
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};
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struct dispc_clock_info {
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/* rates that we get with dividers below */
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unsigned long lck;
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unsigned long pck;
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/* dividers */
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u16 lck_div;
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u16 pck_div;
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};
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struct dsi_clock_info {
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/* rates that we get with dividers below */
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unsigned long fint;
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unsigned long clkin4ddr;
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unsigned long clkin;
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unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
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* OMAP4: PLLx_CLK1 */
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unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
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* OMAP4: PLLx_CLK2 */
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unsigned long lp_clk;
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/* dividers */
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u16 regn;
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u16 regm;
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u16 regm_dispc; /* OMAP3: REGM3
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* OMAP4: REGM4 */
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u16 regm_dsi; /* OMAP3: REGM4
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* OMAP4: REGM5 */
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u16 lp_clk_div;
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u8 highfreq;
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bool use_sys_clk;
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};
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/* HDMI PLL structure */
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struct hdmi_pll_info {
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u16 regn;
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u16 regm;
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u32 regmf;
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u16 regm2;
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u16 regsd;
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u16 dcofreq;
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};
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struct seq_file;
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struct platform_device;
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/* core */
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struct bus_type *dss_get_bus(void);
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struct regulator *dss_get_vdds_dsi(void);
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struct regulator *dss_get_vdds_sdi(void);
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/* display */
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int dss_suspend_all_devices(void);
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int dss_resume_all_devices(void);
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void dss_disable_all_devices(void);
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void dss_init_device(struct platform_device *pdev,
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struct omap_dss_device *dssdev);
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void dss_uninit_device(struct platform_device *pdev,
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struct omap_dss_device *dssdev);
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bool dss_use_replication(struct omap_dss_device *dssdev,
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enum omap_color_mode mode);
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void default_get_overlay_fifo_thresholds(enum omap_plane plane,
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u32 fifo_size, u32 burst_size,
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u32 *fifo_low, u32 *fifo_high);
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/* manager */
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int dss_init_overlay_managers(struct platform_device *pdev);
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void dss_uninit_overlay_managers(struct platform_device *pdev);
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int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
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void dss_setup_partial_planes(struct omap_dss_device *dssdev,
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u16 *x, u16 *y, u16 *w, u16 *h,
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bool enlarge_update_area);
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void dss_start_update(struct omap_dss_device *dssdev);
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/* overlay */
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void dss_init_overlays(struct platform_device *pdev);
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void dss_uninit_overlays(struct platform_device *pdev);
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int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
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void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
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#ifdef L4_EXAMPLE
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void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
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#endif
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void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
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/* DSS */
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int dss_init_platform_driver(void);
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void dss_uninit_platform_driver(void);
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int dss_runtime_get(void);
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void dss_runtime_put(void);
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struct clk *dss_get_ick(void);
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void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
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const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
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void dss_dump_clocks(struct seq_file *s);
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void dss_dump_regs(struct seq_file *s);
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#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
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void dss_debug_dump_clocks(struct seq_file *s);
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#endif
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void dss_sdi_init(u8 datapairs);
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int dss_sdi_enable(void);
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void dss_sdi_disable(void);
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void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
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void dss_select_dsi_clk_source(int dsi_module,
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enum omap_dss_clk_source clk_src);
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void dss_select_lcd_clk_source(enum omap_channel channel,
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enum omap_dss_clk_source clk_src);
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enum omap_dss_clk_source dss_get_dispc_clk_source(void);
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enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
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enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
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void dss_set_venc_output(enum omap_dss_venc_type type);
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void dss_set_dac_pwrdn_bgz(bool enable);
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unsigned long dss_get_dpll4_rate(void);
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int dss_calc_clock_rates(struct dss_clock_info *cinfo);
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int dss_set_clock_div(struct dss_clock_info *cinfo);
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int dss_get_clock_div(struct dss_clock_info *cinfo);
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int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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struct dss_clock_info *dss_cinfo,
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struct dispc_clock_info *dispc_cinfo);
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/* SDI */
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#ifdef CONFIG_OMAP2_DSS_SDI
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int sdi_init(void);
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void sdi_exit(void);
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int sdi_init_display(struct omap_dss_device *display);
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#else
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static inline int sdi_init(void)
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{
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return 0;
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}
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static inline void sdi_exit(void)
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{
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}
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#endif
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/* DSI */
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#ifdef CONFIG_OMAP2_DSS_DSI
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struct dentry;
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struct file_operations;
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int dsi_init_platform_driver(void);
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void dsi_uninit_platform_driver(void);
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int dsi_runtime_get(struct platform_device *dsidev);
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void dsi_runtime_put(struct platform_device *dsidev);
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void dsi_dump_clocks(struct seq_file *s);
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void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
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const struct file_operations *debug_fops);
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void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
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const struct file_operations *debug_fops);
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int dsi_init_display(struct omap_dss_device *display);
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void dsi_irq_handler(void);
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unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
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int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo);
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int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
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unsigned long req_pck, struct dsi_clock_info *cinfo,
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struct dispc_clock_info *dispc_cinfo);
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int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
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bool enable_hsdiv);
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void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
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void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
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u32 fifo_size, u32 burst_size,
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u32 *fifo_low, u32 *fifo_high);
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void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
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void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
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struct platform_device *dsi_get_dsidev_from_id(int module);
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#else
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static inline int dsi_init_platform_driver(void)
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{
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return 0;
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}
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static inline void dsi_uninit_platform_driver(void)
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{
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}
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static inline int dsi_runtime_get(struct platform_device *dsidev)
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{
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return 0;
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}
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static inline void dsi_runtime_put(struct platform_device *dsidev)
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{
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}
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static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
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{
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WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
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return 0;
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}
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static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo)
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{
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WARN("%s: DSI not compiled in\n", __func__);
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return -ENODEV;
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}
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static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
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bool is_tft, unsigned long req_pck,
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struct dsi_clock_info *dsi_cinfo,
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struct dispc_clock_info *dispc_cinfo)
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{
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WARN("%s: DSI not compiled in\n", __func__);
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return -ENODEV;
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}
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static inline int dsi_pll_init(struct platform_device *dsidev,
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bool enable_hsclk, bool enable_hsdiv)
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{
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WARN("%s: DSI not compiled in\n", __func__);
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return -ENODEV;
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}
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static inline void dsi_pll_uninit(struct platform_device *dsidev,
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bool disconnect_lanes)
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{
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}
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static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
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{
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}
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static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
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{
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}
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static inline struct platform_device *dsi_get_dsidev_from_id(int module)
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{
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WARN("%s: DSI not compiled in, returning platform device as NULL\n",
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__func__);
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return NULL;
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}
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#endif
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/* DPI */
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#ifdef CONFIG_OMAP2_DSS_DPI
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int dpi_init(void);
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void dpi_exit(void);
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int dpi_init_display(struct omap_dss_device *dssdev);
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#else
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static inline int dpi_init(void)
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{
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return 0;
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}
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static inline void dpi_exit(void)
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{
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}
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#endif
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/* DISPC */
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int dispc_init_platform_driver(void);
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void dispc_uninit_platform_driver(void);
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void dispc_dump_clocks(struct seq_file *s);
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void dispc_dump_irqs(struct seq_file *s);
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void dispc_dump_regs(struct seq_file *s);
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void dispc_irq_handler(void);
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void dispc_fake_vsync_irq(void);
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int dispc_runtime_get(void);
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void dispc_runtime_put(void);
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void dispc_enable_sidle(void);
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void dispc_disable_sidle(void);
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void dispc_lcd_enable_signal_polarity(bool act_high);
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void dispc_lcd_enable_signal(bool enable);
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void dispc_pck_free_enable(bool enable);
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void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
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void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
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void dispc_set_digit_size(u16 width, u16 height);
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u32 dispc_get_plane_fifo_size(enum omap_plane plane);
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void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
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void dispc_enable_fifomerge(bool enable);
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u32 dispc_get_burst_size(enum omap_plane plane);
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void dispc_enable_cpr(enum omap_channel channel, bool enable);
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void dispc_set_cpr_coef(enum omap_channel channel,
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struct omap_dss_cpr_coefs *coefs);
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void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
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void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
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void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
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void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
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void dispc_set_channel_out(enum omap_plane plane,
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enum omap_channel channel_out);
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void dispc_enable_gamma_table(bool enable);
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int dispc_setup_plane(enum omap_plane plane,
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u32 paddr, u16 screen_width,
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u16 pos_x, u16 pos_y,
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u16 width, u16 height,
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u16 out_width, u16 out_height,
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enum omap_color_mode color_mode,
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bool ilace,
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enum omap_dss_rotation_type rotation_type,
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u8 rotation, bool mirror,
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u8 global_alpha, u8 pre_mult_alpha,
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enum omap_channel channel,
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u32 puv_addr);
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bool dispc_go_busy(enum omap_channel channel);
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void dispc_go(enum omap_channel channel);
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void dispc_enable_channel(enum omap_channel channel, bool enable);
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bool dispc_is_channel_enabled(enum omap_channel channel);
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int dispc_enable_plane(enum omap_plane plane, bool enable);
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void dispc_enable_replication(enum omap_plane plane, bool enable);
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void dispc_set_parallel_interface_mode(enum omap_channel channel,
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enum omap_parallel_interface_mode mode);
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void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
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void dispc_set_lcd_display_type(enum omap_channel channel,
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enum omap_lcd_display_type type);
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void dispc_set_loadmode(enum omap_dss_load_mode mode);
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void dispc_set_default_color(enum omap_channel channel, u32 color);
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u32 dispc_get_default_color(enum omap_channel channel);
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void dispc_set_trans_key(enum omap_channel ch,
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enum omap_dss_trans_key_type type,
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u32 trans_key);
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void dispc_get_trans_key(enum omap_channel ch,
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enum omap_dss_trans_key_type *type,
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u32 *trans_key);
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void dispc_enable_trans_key(enum omap_channel ch, bool enable);
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void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
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bool dispc_trans_key_enabled(enum omap_channel ch);
|
|
bool dispc_alpha_blending_enabled(enum omap_channel ch);
|
|
|
|
bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
|
|
void dispc_set_lcd_timings(enum omap_channel channel,
|
|
struct omap_video_timings *timings);
|
|
unsigned long dispc_fclk_rate(void);
|
|
unsigned long dispc_lclk_rate(enum omap_channel channel);
|
|
unsigned long dispc_pclk_rate(enum omap_channel channel);
|
|
void dispc_set_pol_freq(enum omap_channel channel,
|
|
enum omap_panel_config config, u8 acbi, u8 acb);
|
|
void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
|
|
struct dispc_clock_info *cinfo);
|
|
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
|
|
struct dispc_clock_info *cinfo);
|
|
int dispc_set_clock_div(enum omap_channel channel,
|
|
struct dispc_clock_info *cinfo);
|
|
int dispc_get_clock_div(enum omap_channel channel,
|
|
struct dispc_clock_info *cinfo);
|
|
|
|
|
|
/* VENC */
|
|
#ifdef CONFIG_OMAP2_DSS_VENC
|
|
int venc_init_platform_driver(void);
|
|
void venc_uninit_platform_driver(void);
|
|
void venc_dump_regs(struct seq_file *s);
|
|
int venc_init_display(struct omap_dss_device *display);
|
|
#else
|
|
static inline int venc_init_platform_driver(void)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline void venc_uninit_platform_driver(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/* HDMI */
|
|
#ifdef CONFIG_OMAP4_DSS_HDMI
|
|
int hdmi_init_platform_driver(void);
|
|
void hdmi_uninit_platform_driver(void);
|
|
int hdmi_init_display(struct omap_dss_device *dssdev);
|
|
#else
|
|
static inline int hdmi_init_display(struct omap_dss_device *dssdev)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int hdmi_init_platform_driver(void)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline void hdmi_uninit_platform_driver(void)
|
|
{
|
|
}
|
|
#endif
|
|
int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
|
|
void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
|
|
void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
|
|
int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
int hdmi_panel_init(void);
|
|
void hdmi_panel_exit(void);
|
|
|
|
/* RFBI */
|
|
#ifdef CONFIG_OMAP2_DSS_RFBI
|
|
int rfbi_init_platform_driver(void);
|
|
void rfbi_uninit_platform_driver(void);
|
|
void rfbi_dump_regs(struct seq_file *s);
|
|
int rfbi_init_display(struct omap_dss_device *display);
|
|
#else
|
|
static inline int rfbi_init_platform_driver(void)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline void rfbi_uninit_platform_driver(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
|
|
static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
|
|
{
|
|
int b;
|
|
for (b = 0; b < 32; ++b) {
|
|
if (irqstatus & (1 << b))
|
|
irq_arr[b]++;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#endif
|