forked from Minki/linux
a1c166aca3
The msm8974 pinctrl variant has a couple USB HSIC "glue" registers that let us mux between the pinctrl register settings or the HSIC core settings for the HSIC pins (gpio 144 and gpio 145). Support this method of operation by adding hsic_data and hsic_strobe pins that can select between hsic_ctl and gpio functions. This allows us to toggle the hsic pin configuration over to the HSIC core at runtime. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
116 lines
4.0 KiB
Plaintext
116 lines
4.0 KiB
Plaintext
Qualcomm MSM8974 TLMM block
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Required properties:
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- compatible: "qcom,msm8974-pinctrl"
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- reg: Should be the base address and length of the TLMM block.
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- interrupts: Should be the parent IRQ of the TLMM block.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Should be two.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells : Should be two.
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The first cell is the gpio pin number and the
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second cell is used for optional parameters.
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Qualcomm's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
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Non-empty subnodes must specify the 'pins' property.
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Note that not all properties are valid for all pins.
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Valid values for pins are:
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gpio0-gpio145
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Supports mux, bias and drive-strength
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sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
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Supports bias and drive-strength
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hsic_data, hsic_strobe
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Supports only mux
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Valid values for function are:
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cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
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blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1,
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blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2,
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blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3,
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blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4,
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blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
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blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6,
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blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7,
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blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8,
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blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9,
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blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
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blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11,
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blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12,
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blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
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blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
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sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1,
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cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2,
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cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
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hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
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gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s,
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ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio
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(Note that this is not yet the complete list of functions)
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Example:
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msmgpio: pinctrl@fd510000 {
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compatible = "qcom,msm8974-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_default>;
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uart2_default: uart2_default {
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mux {
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pins = "gpio4", "gpio5";
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function = "blsp_uart2";
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};
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tx {
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pins = "gpio4";
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drive-strength = <4>;
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bias-disable;
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};
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rx {
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pins = "gpio5";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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