linux

History

Linus Torvalds 9e31489029 OpenRISC updates for 4.11 -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJYsL7RAAoJEMOzHC1eZifkXmgP/1HI2c+UeFbV9RVy0AjwQZr0 wgE0qM3ICD1ZV+gNqP4zN0NAIECq1p3qLAV94P+mkfpFc04FZcdysME8ZgvNyzTN BlELpElVKpE9KqlEE7beoybpyc2GlCaieEFB1ouj8lW/nUSc4apqHDh/OVqRssfu QyQ3FDIt6ejvMzq6XRFYJtxL3e8qwAhlIiQBxFYR2b+9MoPgz7Ctf0j0a2SGeTFD UmUz5IGkMXicv91YJeD7vb0iP0ujpbFrXGXneSLS6InzS7h5cZGw1O9B2cyVbBMN unA02MVc/9rz/96J6MIC1GnlI5IuWvsbC0nIRkTukHFVQEcrxmX5BO9iQ47dJ0+n XpCvhRm7djrdkqRsGx8y9xG9hAVXu8a2EyWDz91dJLU8JpTkHkErOLBvmKBEp3kE /K+k75SGIVKpy7hU9buyMmlOhQY09sdzdzfyqCaXD7H4nImShZGmcrZV10mBlZtJ 7k+Ke+fm0EpEewOVyOzwEGjTPr3LDzYCpm2qjOG9/zZd6MX0da8eH2X7DzB9GDWW yR5UiGbtFVE0M13tfE58aVueVRt0o+wLwRZZYur643aLPyypxHWTl3RAhuhv9NzD TaB8n3J6kDt+E5ivzPm2439AM/p9ZcyNGScUSxo84lwXW74ozcpfz029Yvhw52F9 cD4kHEFG7+OYdbZmwV3C =wmBO -----END PGP SIGNATURE----- Merge tag 'openrisc-for-linus' of git://github.com/openrisc/linux Pull OpenRISC updates from Stafford Horne: "Highlights include: - optimized memset and memcpy routines, ~20% boot time saving - support for cpu idling - adding support for l.swa and l.lwa atomic operations (in spec from 2014) - use atomics to implement: bitops, cmpxchg, futex - the atomics are in preparation for SMP support" * tag 'openrisc-for-linus' of git://github.com/openrisc/linux: (25 commits) openrisc: head: Init r0 to 0 on start openrisc: Export ioremap symbols used by modules arch/openrisc/lib/memcpy.c: use correct OR1200 option openrisc: head: Remove unused strings openrisc: head: Move init strings to rodata section openrisc: entry: Fix delay slot detection openrisc: entry: Whitespace and comment cleanups scripts/checkstack.pl: Add openrisc support MAINTAINERS: Add the openrisc official repository openrisc: Add .gitignore openrisc: Add optimized memcpy routine openrisc: Add optimized memset openrisc: Initial support for the idle state openrisc: Fix the bitmask for the unit present register openrisc: remove unnecessary stddef.h include openrisc: add futex_atomic_* implementations openrisc: add optimized atomic operations openrisc: add cmpxchg and xchg implementations openrisc: add atomic bitops openrisc: add l.lwa/l.swa emulation ...		2017-02-24 18:37:03 -08:00
..
boot/dts	openrisc: use new common dtc rule	2012-12-03 17:17:48 -06:00
configs	openrisc: Refresh or1ksim_defconfig for v3.12	2013-11-15 10:37:32 +01:00
include	OpenRISC updates for 4.11	2017-02-24 18:37:03 -08:00
kernel	OpenRISC updates for 4.11	2017-02-24 18:37:03 -08:00
lib	arch/openrisc/lib/memcpy.c: use correct OR1200 option	2017-02-25 05:08:46 +09:00
mm	OpenRISC updates for 4.11	2017-02-24 18:37:03 -08:00
Kconfig	openrisc: use SPARSE_IRQ	2017-02-06 21:50:41 +09:00
Makefile	openrisc: Makefile: append "-D__linux__" to KBUILD_CFLAGS	2013-11-05 16:14:47 +01:00
README.openrisc	openrisc: Updates after openrisc.net has been lost	2016-12-12 23:10:19 +09:00
TODO.openrisc	openrisc: Add optimized memcpy routine	2017-02-25 04:14:36 +09:00

README.openrisc

OpenRISC Linux
==============

This is a port of Linux to the OpenRISC class of microprocessors; the initial
target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).

For information about OpenRISC processors and ongoing development:

	website		http://openrisc.io

For more information about Linux on OpenRISC, please contact South Pole AB.

	email:		info@southpole.se

	website:	http://southpole.se
			http://southpoleconsulting.com

---------------------------------------------------------------------

Build instructions for OpenRISC toolchain and Linux
===================================================

In order to build and run Linux for OpenRISC, you'll need at least a basic
toolchain and, perhaps, the architectural simulator.  Steps to get these bits
in place are outlined here.

1)  The toolchain can be obtained from openrisc.io.  Instructions for building
a toolchain can be found at:

https://github.com/openrisc/tutorials

2) or1ksim (optional)

or1ksim is the architectural simulator which will allow you to actually run
your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.

	git clone https://github.com/openrisc/or1ksim.git

	cd or1ksim
	./configure --prefix=$OPENRISC_PREFIX
	make
	make install

3)  Linux kernel

Build the kernel as usual

	make ARCH=openrisc defconfig
	make ARCH=openrisc

4)  Run in architectural simulator

Grab the or1ksim platform configuration file (from the or1ksim source) and
together with your freshly built vmlinux, run your kernel with the following
incantation:

	sim -f arch/openrisc/or1ksim.cfg vmlinux

---------------------------------------------------------------------

Terminology
===========

In the code, the following particles are used on symbols to limit the scope
to more or less specific processor implementations:

openrisc: the OpenRISC class of processors
or1k:     the OpenRISC 1000 family of processors
or1200:   the OpenRISC 1200 processor

---------------------------------------------------------------------

History
========

18. 11. 2003	Matjaz Breskvar (phoenix@bsemi.com)
	initial port of linux to OpenRISC/or32 architecture.
        all the core stuff is implemented and seams usable.

08. 12. 2003	Matjaz Breskvar (phoenix@bsemi.com)
	complete change of TLB miss handling.
	rewrite of exceptions handling.
	fully functional sash-3.6 in default initrd.
	a much improved version with changes all around.

10. 04. 2004	Matjaz Breskvar (phoenix@bsemi.com)
	alot of bugfixes all over.
	ethernet support, functional http and telnet servers.
	running many standard linux apps.

26. 06. 2004	Matjaz Breskvar (phoenix@bsemi.com)
	port to 2.6.x

30. 11. 2004	Matjaz Breskvar (phoenix@bsemi.com)
	lots of bugfixes and enhancments.
	added opencores framebuffer driver.

09. 10. 2010    Jonas Bonn (jonas@southpole.se)
	major rewrite to bring up to par with upstream Linux 2.6.36