forked from Minki/linux
2cc0c0b5cd
Adjust to preferred code names. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
569 lines
14 KiB
C
569 lines
14 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "linux/delay.h"
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include "cgs_common.h"
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#include "power_state.h"
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#include "hwmgr.h"
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#include "pppcielanes.h"
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#include "pp_debug.h"
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#include "ppatomctrl.h"
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extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
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int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
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{
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struct pp_hwmgr *hwmgr;
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if ((handle == NULL) || (pp_init == NULL))
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return -EINVAL;
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hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
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if (hwmgr == NULL)
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return -ENOMEM;
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handle->hwmgr = hwmgr;
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hwmgr->smumgr = handle->smu_mgr;
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hwmgr->device = pp_init->device;
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hwmgr->chip_family = pp_init->chip_family;
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hwmgr->chip_id = pp_init->chip_id;
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hwmgr->hw_revision = pp_init->rev_id;
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hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
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hwmgr->power_source = PP_PowerSource_AC;
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switch (hwmgr->chip_family) {
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case AMD_FAMILY_CZ:
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cz_hwmgr_init(hwmgr);
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break;
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case AMD_FAMILY_VI:
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switch (hwmgr->chip_id) {
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case CHIP_TONGA:
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tonga_hwmgr_init(hwmgr);
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break;
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case CHIP_FIJI:
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fiji_hwmgr_init(hwmgr);
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break;
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case CHIP_POLARIS11:
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case CHIP_POLARIS10:
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polaris10_hwmgr_init(hwmgr);
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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phm_init_dynamic_caps(hwmgr);
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return 0;
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}
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int hwmgr_fini(struct pp_hwmgr *hwmgr)
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{
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if (hwmgr == NULL || hwmgr->ps == NULL)
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return -EINVAL;
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kfree(hwmgr->ps);
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kfree(hwmgr);
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return 0;
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}
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int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
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{
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int result;
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unsigned int i;
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unsigned int table_entries;
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struct pp_power_state *state;
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int size;
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if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
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return -EINVAL;
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if (hwmgr->hwmgr_func->get_power_state_size == NULL)
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return -EINVAL;
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hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
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hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
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sizeof(struct pp_power_state);
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hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
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if (hwmgr->ps == NULL)
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return -ENOMEM;
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state = hwmgr->ps;
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for (i = 0; i < table_entries; i++) {
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result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
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if (state->classification.flags & PP_StateClassificationFlag_Boot) {
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hwmgr->boot_ps = state;
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hwmgr->current_ps = hwmgr->request_ps = state;
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}
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state->id = i + 1; /* assigned unique num for every power state id */
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if (state->classification.flags & PP_StateClassificationFlag_Uvd)
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hwmgr->uvd_ps = state;
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state = (struct pp_power_state *)((unsigned long)state + size);
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}
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return 0;
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}
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/**
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* Returns once the part of the register indicated by the mask has
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* reached the given value.
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*/
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int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
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uint32_t value, uint32_t mask)
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{
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uint32_t i;
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uint32_t cur_value;
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if (hwmgr == NULL || hwmgr->device == NULL) {
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printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
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return -EINVAL;
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}
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for (i = 0; i < hwmgr->usec_timeout; i++) {
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cur_value = cgs_read_register(hwmgr->device, index);
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if ((cur_value & mask) == (value & mask))
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break;
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udelay(1);
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}
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/* timeout means wrong logic*/
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if (i == hwmgr->usec_timeout)
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return -1;
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return 0;
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}
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int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
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uint32_t index, uint32_t value, uint32_t mask)
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{
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uint32_t i;
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uint32_t cur_value;
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if (hwmgr == NULL || hwmgr->device == NULL) {
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printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
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return -EINVAL;
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}
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for (i = 0; i < hwmgr->usec_timeout; i++) {
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cur_value = cgs_read_register(hwmgr->device, index);
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if ((cur_value & mask) != (value & mask))
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break;
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udelay(1);
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}
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/* timeout means wrong logic*/
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if (i == hwmgr->usec_timeout)
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return -1;
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return 0;
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}
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/**
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* Returns once the part of the register indicated by the mask has
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* reached the given value.The indirect space is described by giving
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* the memory-mapped index of the indirect index register.
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*/
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void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
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uint32_t indirect_port,
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uint32_t index,
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uint32_t value,
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uint32_t mask)
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{
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if (hwmgr == NULL || hwmgr->device == NULL) {
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printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
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return;
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}
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cgs_write_register(hwmgr->device, indirect_port, index);
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phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
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}
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void phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
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uint32_t indirect_port,
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uint32_t index,
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uint32_t value,
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uint32_t mask)
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{
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if (hwmgr == NULL || hwmgr->device == NULL) {
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printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
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return;
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}
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cgs_write_register(hwmgr->device, indirect_port, index);
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phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
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value, mask);
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}
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bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
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{
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return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
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}
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bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
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{
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return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
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}
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int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
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{
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uint32_t i, j;
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uint16_t vvalue;
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bool found = false;
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struct pp_atomctrl_voltage_table *table;
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"Voltage Table empty.", return -EINVAL);
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table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
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GFP_KERNEL);
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if (NULL == table)
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return -EINVAL;
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table->mask_low = vol_table->mask_low;
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table->phase_delay = vol_table->phase_delay;
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for (i = 0; i < vol_table->count; i++) {
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vvalue = vol_table->entries[i].value;
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found = false;
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for (j = 0; j < table->count; j++) {
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if (vvalue == table->entries[j].value) {
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found = true;
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break;
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}
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}
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if (!found) {
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table->entries[table->count].value = vvalue;
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table->entries[table->count].smio_low =
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vol_table->entries[i].smio_low;
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table->count++;
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}
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}
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memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
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kfree(table);
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return 0;
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}
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int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
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phm_ppt_v1_clock_voltage_dependency_table *dep_table)
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{
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uint32_t i;
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int result;
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PP_ASSERT_WITH_CODE((0 != dep_table->count),
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"Voltage Dependency Table empty.", return -EINVAL);
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"vol_table empty.", return -EINVAL);
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vol_table->mask_low = 0;
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vol_table->phase_delay = 0;
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vol_table->count = dep_table->count;
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for (i = 0; i < dep_table->count; i++) {
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vol_table->entries[i].value = dep_table->entries[i].mvdd;
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vol_table->entries[i].smio_low = 0;
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}
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result = phm_trim_voltage_table(vol_table);
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PP_ASSERT_WITH_CODE((0 == result),
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"Failed to trim MVDD table.", return result);
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return 0;
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}
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int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
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phm_ppt_v1_clock_voltage_dependency_table *dep_table)
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{
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uint32_t i;
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int result;
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PP_ASSERT_WITH_CODE((0 != dep_table->count),
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"Voltage Dependency Table empty.", return -EINVAL);
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"vol_table empty.", return -EINVAL);
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vol_table->mask_low = 0;
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vol_table->phase_delay = 0;
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vol_table->count = dep_table->count;
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for (i = 0; i < dep_table->count; i++) {
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vol_table->entries[i].value = dep_table->entries[i].vddci;
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vol_table->entries[i].smio_low = 0;
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}
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result = phm_trim_voltage_table(vol_table);
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PP_ASSERT_WITH_CODE((0 == result),
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"Failed to trim VDDCI table.", return result);
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return 0;
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}
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int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
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phm_ppt_v1_voltage_lookup_table *lookup_table)
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{
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int i = 0;
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PP_ASSERT_WITH_CODE((0 != lookup_table->count),
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"Voltage Lookup Table empty.", return -EINVAL);
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"vol_table empty.", return -EINVAL);
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vol_table->mask_low = 0;
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vol_table->phase_delay = 0;
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vol_table->count = lookup_table->count;
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for (i = 0; i < vol_table->count; i++) {
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vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
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vol_table->entries[i].smio_low = 0;
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}
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return 0;
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}
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void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
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struct pp_atomctrl_voltage_table *vol_table)
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{
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unsigned int i, diff;
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if (vol_table->count <= max_vol_steps)
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return;
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diff = vol_table->count - max_vol_steps;
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for (i = 0; i < max_vol_steps; i++)
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vol_table->entries[i] = vol_table->entries[i + diff];
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vol_table->count = max_vol_steps;
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return;
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}
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int phm_reset_single_dpm_table(void *table,
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uint32_t count, int max)
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{
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int i;
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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PP_ASSERT_WITH_CODE(count <= max,
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"Fatal error, can not set up single DPM table entries to exceed max number!",
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);
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dpm_table->count = count;
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for (i = 0; i < max; i++)
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dpm_table->dpm_level[i].enabled = false;
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return 0;
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}
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void phm_setup_pcie_table_entry(
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void *table,
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uint32_t index, uint32_t pcie_gen,
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uint32_t pcie_lanes)
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{
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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dpm_table->dpm_level[index].value = pcie_gen;
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dpm_table->dpm_level[index].param1 = pcie_lanes;
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dpm_table->dpm_level[index].enabled = 1;
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}
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int32_t phm_get_dpm_level_enable_mask_value(void *table)
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{
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int32_t i;
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int32_t mask = 0;
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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for (i = dpm_table->count; i > 0; i--) {
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mask = mask << 1;
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if (dpm_table->dpm_level[i - 1].enabled)
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mask |= 0x1;
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else
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mask &= 0xFFFFFFFE;
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}
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return mask;
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}
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uint8_t phm_get_voltage_index(
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struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
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{
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uint8_t count = (uint8_t) (lookup_table->count);
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uint8_t i;
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PP_ASSERT_WITH_CODE((NULL != lookup_table),
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"Lookup Table empty.", return 0);
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PP_ASSERT_WITH_CODE((0 != count),
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"Lookup Table empty.", return 0);
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for (i = 0; i < lookup_table->count; i++) {
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/* find first voltage equal or bigger than requested */
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if (lookup_table->entries[i].us_vdd >= voltage)
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return i;
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}
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/* voltage is bigger than max voltage in the table */
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return i - 1;
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}
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uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
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{
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uint32_t i;
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for (i = 0; i < vddci_table->count; i++) {
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if (vddci_table->entries[i].value >= vddci)
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return vddci_table->entries[i].value;
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}
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PP_ASSERT_WITH_CODE(false,
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"VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
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return vddci_table->entries[i].value);
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}
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int phm_find_boot_level(void *table,
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uint32_t value, uint32_t *boot_level)
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{
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int result = -EINVAL;
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uint32_t i;
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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for (i = 0; i < dpm_table->count; i++) {
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if (value == dpm_table->dpm_level[i].value) {
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*boot_level = i;
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result = 0;
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}
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}
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return result;
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}
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int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
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phm_ppt_v1_voltage_lookup_table *lookup_table,
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uint16_t virtual_voltage_id, int32_t *sclk)
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{
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uint8_t entryId;
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uint8_t voltageId;
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
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/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
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for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
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voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
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if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
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break;
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}
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PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
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|
"Can't find requested voltage id in vdd_dep_on_sclk table!",
|
|
return -EINVAL;
|
|
);
|
|
|
|
*sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Initialize Dynamic State Adjustment Rule Settings
|
|
*
|
|
* @param hwmgr the address of the powerplay hardware manager.
|
|
*/
|
|
int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
|
|
{
|
|
uint32_t table_size;
|
|
struct phm_clock_voltage_dependency_table *table_clk_vlt;
|
|
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
|
|
|
|
/* initialize vddc_dep_on_dal_pwrl table */
|
|
table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
|
|
table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
|
|
|
|
if (NULL == table_clk_vlt) {
|
|
printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
|
|
return -ENOMEM;
|
|
} else {
|
|
table_clk_vlt->count = 4;
|
|
table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
|
|
table_clk_vlt->entries[0].v = 0;
|
|
table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
|
|
table_clk_vlt->entries[1].v = 720;
|
|
table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
|
|
table_clk_vlt->entries[2].v = 810;
|
|
table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
|
|
table_clk_vlt->entries[3].v = 900;
|
|
pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
|
|
hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
|
|
{
|
|
if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
|
|
kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
|
|
hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
|
|
}
|
|
|
|
if (NULL != hwmgr->backend) {
|
|
kfree(hwmgr->backend);
|
|
hwmgr->backend = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
|
|
{
|
|
uint32_t level = 0;
|
|
|
|
while (0 == (mask & (1 << level)))
|
|
level++;
|
|
|
|
return level;
|
|
}
|