9e1bae6d67
Move QSERDES V2 registers to the separate header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-9-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
84 lines
3.3 KiB
C
84 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_COM_H_
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#define QCOM_PHY_QMP_QSERDES_COM_H_
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/* Only for QMP V2 PHY - QSERDES COM registers */
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#define QSERDES_COM_BG_TIMER 0x00c
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#define QSERDES_COM_SSC_EN_CENTER 0x010
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#define QSERDES_COM_SSC_ADJ_PER1 0x014
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#define QSERDES_COM_SSC_ADJ_PER2 0x018
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#define QSERDES_COM_SSC_PER1 0x01c
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#define QSERDES_COM_SSC_PER2 0x020
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#define QSERDES_COM_SSC_STEP_SIZE1 0x024
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#define QSERDES_COM_SSC_STEP_SIZE2 0x028
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
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#define QSERDES_COM_CLK_ENABLE1 0x038
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#define QSERDES_COM_SYS_CLK_CTRL 0x03c
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#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
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#define QSERDES_COM_PLL_IVCO 0x048
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#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
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#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
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#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
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#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
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#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
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#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
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#define QSERDES_COM_BG_TRIM 0x070
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#define QSERDES_COM_CLK_EP_DIV 0x074
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#define QSERDES_COM_CP_CTRL_MODE0 0x078
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#define QSERDES_COM_CP_CTRL_MODE1 0x07c
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#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
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#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
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#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
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#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
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#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
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#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
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#define QSERDES_COM_RESETSM_CNTRL 0x0b4
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#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
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#define QSERDES_COM_RESTRIM_CTRL 0x0bc
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#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
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#define QSERDES_COM_LOCK_CMP_EN 0x0c8
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#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
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#define QSERDES_COM_DEC_START_MODE0 0x0d0
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#define QSERDES_COM_DEC_START_MODE1 0x0d4
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#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
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#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
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#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
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#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
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#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
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#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
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#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
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#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
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#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
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#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
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#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
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#define QSERDES_COM_VCO_TUNE_CTRL 0x124
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#define QSERDES_COM_VCO_TUNE_MAP 0x128
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#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
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#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
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#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
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#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
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#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
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#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
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#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
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#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
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#define QSERDES_COM_BG_CTRL 0x170
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#define QSERDES_COM_CLK_SELECT 0x174
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#define QSERDES_COM_HSCLK_SEL 0x178
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#define QSERDES_COM_CORECLK_DIV 0x184
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#define QSERDES_COM_CORE_CLK_EN 0x18c
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#define QSERDES_COM_C_READY_STATUS 0x190
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#define QSERDES_COM_CMN_CONFIG 0x194
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#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
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#define QSERDES_COM_DEBUG_BUS0 0x1a0
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#define QSERDES_COM_DEBUG_BUS1 0x1a4
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#define QSERDES_COM_DEBUG_BUS2 0x1a8
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#define QSERDES_COM_DEBUG_BUS3 0x1ac
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#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
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#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
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#endif
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