forked from Minki/linux
48e304cc19
This was a SoC issue on LX2160A Rev1.0. eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] must be set to 0 to get 4 delay cells in the pulse width detection logic for eMMC HS400 mode. Otherwise it would cause unexpected HS400 issue. This patch is to clear this bit always for affected SoC when reset for all, since this bit doesn't affect other speed modes. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
/*
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* Freescale eSDHC controller driver generics for OF and pltfm.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Copyright (c) 2010 Pengutronix e.K.
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* Author: Wolfram Sang <w.sang@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
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#define _DRIVERS_MMC_SDHCI_ESDHC_H
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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*/
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#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
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SDHCI_QUIRK_32BIT_DMA_ADDR | \
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SDHCI_QUIRK_NO_BUSY_IRQ | \
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
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SDHCI_QUIRK_PIO_NEEDS_DELAY | \
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SDHCI_QUIRK_NO_HISPD_BIT)
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/* pltfm-specific */
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#define ESDHC_HOST_CONTROL_LE 0x20
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/*
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* eSDHC register definition
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*/
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/* Present State Register */
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#define ESDHC_PRSSTAT 0x24
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#define ESDHC_CLOCK_STABLE 0x00000008
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/* Protocol Control Register */
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#define ESDHC_PROCTL 0x28
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#define ESDHC_VOLT_SEL 0x00000400
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#define ESDHC_CTRL_4BITBUS (0x1 << 1)
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#define ESDHC_CTRL_8BITBUS (0x2 << 1)
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#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
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#define ESDHC_HOST_CONTROL_RES 0x01
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/* System Control Register */
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_SDCLKEN 0x00000008
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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/* Host Controller Capabilities Register 2 */
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#define ESDHC_CAPABILITIES_1 0x114
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/* Tuning Block Control Register */
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#define ESDHC_TBCTL 0x120
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#define ESDHC_HS400_WNDW_ADJUST 0x00000040
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#define ESDHC_HS400_MODE 0x00000010
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#define ESDHC_TB_EN 0x00000004
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#define ESDHC_TBPTR 0x128
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/* SD Clock Control Register */
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#define ESDHC_SDCLKCTL 0x144
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#define ESDHC_LPBK_CLK_SEL 0x80000000
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#define ESDHC_CMD_CLK_CTL 0x00008000
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/* SD Timing Control Register */
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#define ESDHC_SDTIMNGCTL 0x148
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#define ESDHC_FLW_CTL_BG 0x00008000
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/* DLL Config 0 Register */
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#define ESDHC_DLLCFG0 0x160
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#define ESDHC_DLL_ENABLE 0x80000000
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#define ESDHC_DLL_FREQ_SEL 0x08000000
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/* DLL Config 1 Register */
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#define ESDHC_DLLCFG1 0x164
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#define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
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/* DLL Status 0 Register */
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#define ESDHC_DLLSTAT0 0x170
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#define ESDHC_DLL_STS_SLV_LOCK 0x08000000
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/* Control Register for DMA transfer */
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
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#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
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#define ESDHC_DMA_SNOOP 0x00000040
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#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
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