forked from Minki/linux
9ded63aaf8
The system register encoding generated by sys_reg() works only for MRS/MSR(Register) operations, as we hardcode Bit20 to 1 in mrs_s/msr_s mask. This makes it unusable for generating instructions accessing registers with Op0 < 2(e.g, PSTATE.x with Op0=0). As per ARMv8 ARM, (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", C5.2, version:ARM DDI 0487A.f), the instruction encoding reserves bits [20-19] for Op0. This patch generalises the sys_reg, mrs_s and msr_s macros, so that we could use them to access any of the supported system register. Cc: James Morse <james.morse@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
/*
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* Macros for accessing system registers with older binutils.
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*
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* Copyright (C) 2014 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SYSREG_H
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#define __ASM_SYSREG_H
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#define SCTLR_EL1_CP15BEN (0x1 << 5)
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#define SCTLR_EL1_SED (0x1 << 8)
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/*
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* ARMv8 ARM reserves the following encoding for system registers:
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* (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
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* C5.2, version:ARM DDI 0487A.f)
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* [20-19] : Op0
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* [18-16] : Op1
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* [15-12] : CRn
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* [11-8] : CRm
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* [7-5] : Op2
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*/
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#define sys_reg(op0, op1, crn, crm, op2) \
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((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
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#ifdef __ASSEMBLY__
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.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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.equ __reg_num_x\num, \num
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.endr
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.equ __reg_num_xzr, 31
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.macro mrs_s, rt, sreg
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.inst 0xd5200000|(\sreg)|(__reg_num_\rt)
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.endm
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.macro msr_s, sreg, rt
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.inst 0xd5000000|(\sreg)|(__reg_num_\rt)
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.endm
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#else
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asm(
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" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
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" .equ __reg_num_x\\num, \\num\n"
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" .endr\n"
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" .equ __reg_num_xzr, 31\n"
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"\n"
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" .macro mrs_s, rt, sreg\n"
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" .inst 0xd5200000|(\\sreg)|(__reg_num_\\rt)\n"
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" .endm\n"
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"\n"
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" .macro msr_s, sreg, rt\n"
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" .inst 0xd5000000|(\\sreg)|(__reg_num_\\rt)\n"
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" .endm\n"
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);
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static inline void config_sctlr_el1(u32 clear, u32 set)
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{
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u32 val;
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asm volatile("mrs %0, sctlr_el1" : "=r" (val));
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val &= ~clear;
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val |= set;
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asm volatile("msr sctlr_el1, %0" : : "r" (val));
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}
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#endif
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#endif /* __ASM_SYSREG_H */
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