Suzuki K Poulose 9dbd5bb25c arm64: Refactor sysinstr exception handling ... Right now we trap some of the user space data cache operations based on a few Errata (ARM 819472, 826319, 827319 and 824069). We need to trap userspace access to CTR_EL0, if we detect mismatched cache line size. Since both these traps share the EC, refactor the handler a little bit to make it a bit more reader friendly. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>		2016-09-09 15:03:29 +01:00
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asm	arm64: Refactor sysinstr exception handling	2016-09-09 15:03:29 +01:00
uapi/asm	arm64 fixes:	2016-08-06 08:58:59 -04:00