424d6d1a9a
Add adsp clock on/off support on mt8195 platform. Signed-off-by: YC Hung <yc.hung@mediatek.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20211118100749.54628-8-daniel.baluta@oss.nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Corporation. All rights reserved.
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*/
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#ifndef __MTK_ADSP_HELPER_H__
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#define __MTK_ADSP_HELPER_H__
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/*
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* Global important adsp data structure.
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*/
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#define DSP_MBOX_NUM 3
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struct mtk_adsp_chip_info {
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phys_addr_t pa_sram;
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phys_addr_t pa_dram; /* adsp dram physical base */
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phys_addr_t pa_shared_dram; /* adsp dram physical base */
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phys_addr_t pa_cfgreg;
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phys_addr_t pa_mboxreg[DSP_MBOX_NUM];
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u32 sramsize;
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u32 dramsize;
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u32 cfgregsize;
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void __iomem *va_sram; /* corresponding to pa_sram */
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void __iomem *va_dram; /* corresponding to pa_dram */
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void __iomem *va_cfgreg;
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void __iomem *va_mboxreg[DSP_MBOX_NUM];
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void __iomem *shared_sram; /* part of va_sram */
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void __iomem *shared_dram; /* part of va_dram */
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phys_addr_t adsp_bootup_addr;
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int dram_offset; /*dram offset between system and dsp view*/
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};
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struct adsp_priv {
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struct device *dev;
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struct snd_sof_dev *sdev;
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/* DSP IPC handler */
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struct mbox_controller *adsp_mbox;
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struct mtk_adsp_chip_info *adsp;
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struct clk **clk;
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u32 (*ap2adsp_addr)(u32 addr, void *data);
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u32 (*adsp2ap_addr)(u32 addr, void *data);
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void *private_data;
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};
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#endif
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