forked from Minki/linux
9d32d1653d
At this time, the HDMI port is enabled, and the DIP control register
specification says we need to disable the port *before* disabling the
DIPs. Also, while doing this we risk telling the HW to send the AVI
DIPs once (not every VSync), which really seems to confuse the HW and
trigger bugs where the DIPs are not sent.
This code was here just to set the DIP register to a 'known state'
before using it, but since now the set_infoframes functions already
set the control registers to a known state, this code can go away.
Also, the previous code disables *all* the DIP registers for *each*
HDMI port, so we end disabling each DIP register more than once.
This patch solves a problem I can reproduce on my IVB machine. When I
boot it with just a single HDMI monitor, the AVI InfoFrames are not
sent. With this patch, the InfoFrames are sent. Previously, I wrote a
patch to 'touch the DIP registers after we enable the HDMI port' to
solve this same problem, but that patch doesn't seem to be needed
anymore after this patch.
All this patch does is revert a chunk of the following commit:
commit 64a8fc0145
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Thu Sep 22 11:16:00 2011 +0530
drm/i915: fix ILK+ infoframe support
So bugs that can be bisected to that commit may be fixed now.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43256
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
932 lines
26 KiB
C
932 lines
26 KiB
C
/*
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* Copyright 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Jesse Barnes <jesse.barnes@intel.com>
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*/
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include "drmP.h"
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#include "drm.h"
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#include "drm_crtc.h"
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#include "drm_edid.h"
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#include "intel_drv.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct intel_hdmi, base.base);
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}
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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
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{
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return container_of(intel_attached_encoder(connector),
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struct intel_hdmi, base);
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}
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void intel_dip_infoframe_csum(struct dip_infoframe *frame)
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{
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uint8_t *data = (uint8_t *)frame;
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uint8_t sum = 0;
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unsigned i;
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frame->checksum = 0;
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frame->ecc = 0;
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for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
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sum += data[i];
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frame->checksum = 0x100 - sum;
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}
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static u32 g4x_infoframe_index(struct dip_infoframe *frame)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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return VIDEO_DIP_SELECT_AVI;
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case DIP_TYPE_SPD:
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return VIDEO_DIP_SELECT_SPD;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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return 0;
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}
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}
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static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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return VIDEO_DIP_ENABLE_AVI;
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case DIP_TYPE_SPD:
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return VIDEO_DIP_ENABLE_SPD;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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return 0;
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}
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}
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static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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return VIDEO_DIP_ENABLE_AVI_HSW;
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case DIP_TYPE_SPD:
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return VIDEO_DIP_ENABLE_SPD_HSW;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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return 0;
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}
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}
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static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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return HSW_TVIDEO_DIP_AVI_DATA(pipe);
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case DIP_TYPE_SPD:
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return HSW_TVIDEO_DIP_SPD_DATA(pipe);
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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return 0;
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}
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}
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static void g4x_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val = I915_READ(VIDEO_DIP_CTL);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(VIDEO_DIP_CTL, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VIDEO_DIP_DATA, *data);
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data++;
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}
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(VIDEO_DIP_CTL, val);
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}
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static void ibx_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(reg, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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}
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static void cpt_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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/* The DIP control register spec says that we need to update the AVI
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* infoframe without clearing its enable bit */
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if (frame->type != DIP_TYPE_AVI)
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(reg, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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}
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static void vlv_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(reg, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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}
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static void hsw_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
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unsigned int i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(ctl_reg);
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if (data_reg == 0)
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return;
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val &= ~hsw_infoframe_enable(frame);
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I915_WRITE(ctl_reg, val);
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for (i = 0; i < len; i += 4) {
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I915_WRITE(data_reg + i, *data);
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data++;
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}
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val |= hsw_infoframe_enable(frame);
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I915_WRITE(ctl_reg, val);
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}
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static void intel_set_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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intel_dip_infoframe_csum(frame);
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intel_hdmi->write_infoframe(encoder, frame);
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}
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static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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{
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struct dip_infoframe avi_if = {
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.type = DIP_TYPE_AVI,
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.ver = DIP_VERSION_AVI,
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.len = DIP_LEN_AVI,
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};
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
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avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
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intel_set_infoframe(encoder, &avi_if);
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}
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static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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{
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struct dip_infoframe spd_if;
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memset(&spd_if, 0, sizeof(spd_if));
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spd_if.type = DIP_TYPE_SPD;
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spd_if.ver = DIP_VERSION_SPD;
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spd_if.len = DIP_LEN_SPD;
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strcpy(spd_if.body.spd.vn, "Intel");
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strcpy(spd_if.body.spd.pd, "Integrated gfx");
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spd_if.body.spd.sdi = DIP_SPD_PC;
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intel_set_infoframe(encoder, &spd_if);
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}
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static void g4x_set_infoframes(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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u32 reg = VIDEO_DIP_CTL;
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u32 val = I915_READ(reg);
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u32 port;
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/* If the registers were not initialized yet, they might be zeroes,
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* which means we're selecting the AVI DIP and we're setting its
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* frequency to once. This seems to really confuse the HW and make
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* things stop working (the register spec says the AVI always needs to
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* be sent every VSync). So here we avoid writing to the register more
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* than we need and also explicitly select the AVI DIP and explicitly
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* set its frequency to every VSync. Avoiding to write it twice seems to
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* be enough to solve the problem, but being defensive shouldn't hurt us
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* either. */
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val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
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if (!intel_hdmi->has_hdmi_sink) {
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if (!(val & VIDEO_DIP_ENABLE))
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return;
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val &= ~VIDEO_DIP_ENABLE;
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I915_WRITE(reg, val);
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return;
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}
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switch (intel_hdmi->sdvox_reg) {
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case SDVOB:
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port = VIDEO_DIP_PORT_B;
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break;
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case SDVOC:
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port = VIDEO_DIP_PORT_C;
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break;
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default:
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return;
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}
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if (port != (val & VIDEO_DIP_PORT_MASK)) {
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if (val & VIDEO_DIP_ENABLE) {
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val &= ~VIDEO_DIP_ENABLE;
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I915_WRITE(reg, val);
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}
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val &= ~VIDEO_DIP_PORT_MASK;
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val |= port;
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}
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val |= VIDEO_DIP_ENABLE;
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val &= ~VIDEO_DIP_ENABLE_VENDOR;
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I915_WRITE(reg, val);
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intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
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intel_hdmi_set_spd_infoframe(encoder);
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}
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static void ibx_set_infoframes(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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u32 port;
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/* See the big comment in g4x_set_infoframes() */
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val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
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if (!intel_hdmi->has_hdmi_sink) {
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if (!(val & VIDEO_DIP_ENABLE))
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return;
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val &= ~VIDEO_DIP_ENABLE;
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I915_WRITE(reg, val);
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return;
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}
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|
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switch (intel_hdmi->sdvox_reg) {
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case HDMIB:
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port = VIDEO_DIP_PORT_B;
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break;
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case HDMIC:
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port = VIDEO_DIP_PORT_C;
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break;
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|
case HDMID:
|
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port = VIDEO_DIP_PORT_D;
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break;
|
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default:
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return;
|
|
}
|
|
|
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if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
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if (val & VIDEO_DIP_ENABLE) {
|
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val &= ~VIDEO_DIP_ENABLE;
|
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I915_WRITE(reg, val);
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}
|
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val &= ~VIDEO_DIP_PORT_MASK;
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val |= port;
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}
|
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val |= VIDEO_DIP_ENABLE;
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val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
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VIDEO_DIP_ENABLE_GCP);
|
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|
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I915_WRITE(reg, val);
|
|
|
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intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
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intel_hdmi_set_spd_infoframe(encoder);
|
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}
|
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|
|
static void cpt_set_infoframes(struct drm_encoder *encoder,
|
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struct drm_display_mode *adjusted_mode)
|
|
{
|
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
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u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
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u32 val = I915_READ(reg);
|
|
|
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/* See the big comment in g4x_set_infoframes() */
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val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
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if (!(val & VIDEO_DIP_ENABLE))
|
|
return;
|
|
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
|
|
I915_WRITE(reg, val);
|
|
return;
|
|
}
|
|
|
|
/* Set both together, unset both together: see the spec. */
|
|
val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
|
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val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
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VIDEO_DIP_ENABLE_GCP);
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|
|
I915_WRITE(reg, val);
|
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|
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intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
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intel_hdmi_set_spd_infoframe(encoder);
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}
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|
|
|
static void vlv_set_infoframes(struct drm_encoder *encoder,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
|
|
u32 val = I915_READ(reg);
|
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
return;
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
I915_WRITE(reg, val);
|
|
return;
|
|
}
|
|
|
|
val |= VIDEO_DIP_ENABLE;
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
VIDEO_DIP_ENABLE_GCP);
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
}
|
|
|
|
static void hsw_set_infoframes(struct drm_encoder *encoder,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
|
|
u32 val = I915_READ(reg);
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
I915_WRITE(reg, 0);
|
|
return;
|
|
}
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
|
|
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
}
|
|
|
|
static void intel_hdmi_mode_set(struct drm_encoder *encoder,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
u32 sdvox;
|
|
|
|
sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
|
|
if (!HAS_PCH_SPLIT(dev))
|
|
sdvox |= intel_hdmi->color_range;
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
|
|
|
|
if (intel_crtc->bpp > 24)
|
|
sdvox |= COLOR_FORMAT_12bpc;
|
|
else
|
|
sdvox |= COLOR_FORMAT_8bpc;
|
|
|
|
/* Required on CPT */
|
|
if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
|
|
sdvox |= HDMI_MODE_SELECT;
|
|
|
|
if (intel_hdmi->has_audio) {
|
|
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
|
|
pipe_name(intel_crtc->pipe));
|
|
sdvox |= SDVO_AUDIO_ENABLE;
|
|
sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
|
|
intel_write_eld(encoder, adjusted_mode);
|
|
}
|
|
|
|
if (HAS_PCH_CPT(dev))
|
|
sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
|
|
else if (intel_crtc->pipe == 1)
|
|
sdvox |= SDVO_PIPE_B_SELECT;
|
|
|
|
I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
|
|
|
intel_hdmi->set_infoframes(encoder, adjusted_mode);
|
|
}
|
|
|
|
static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
u32 temp;
|
|
u32 enable_bits = SDVO_ENABLE;
|
|
|
|
if (intel_hdmi->has_audio)
|
|
enable_bits |= SDVO_AUDIO_ENABLE;
|
|
|
|
temp = I915_READ(intel_hdmi->sdvox_reg);
|
|
|
|
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
|
|
* we do this anyway which shows more stable in testing.
|
|
*/
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
|
}
|
|
|
|
if (mode != DRM_MODE_DPMS_ON) {
|
|
temp &= ~enable_bits;
|
|
} else {
|
|
temp |= enable_bits;
|
|
}
|
|
|
|
I915_WRITE(intel_hdmi->sdvox_reg, temp);
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
|
|
|
/* HW workaround, need to write this twice for issue that may result
|
|
* in first write getting masked.
|
|
*/
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(intel_hdmi->sdvox_reg, temp);
|
|
POSTING_READ(intel_hdmi->sdvox_reg);
|
|
}
|
|
}
|
|
|
|
static int intel_hdmi_mode_valid(struct drm_connector *connector,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
if (mode->clock > 165000)
|
|
return MODE_CLOCK_HIGH;
|
|
if (mode->clock < 20000)
|
|
return MODE_CLOCK_LOW;
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
return MODE_NO_DBLESCAN;
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
|
|
{
|
|
struct drm_device *dev = intel_hdmi->base.base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
uint32_t bit;
|
|
|
|
switch (intel_hdmi->sdvox_reg) {
|
|
case SDVOB:
|
|
bit = HDMIB_HOTPLUG_LIVE_STATUS;
|
|
break;
|
|
case SDVOC:
|
|
bit = HDMIC_HOTPLUG_LIVE_STATUS;
|
|
break;
|
|
default:
|
|
bit = 0;
|
|
break;
|
|
}
|
|
|
|
return I915_READ(PORT_HOTPLUG_STAT) & bit;
|
|
}
|
|
|
|
static enum drm_connector_status
|
|
intel_hdmi_detect(struct drm_connector *connector, bool force)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
struct edid *edid;
|
|
enum drm_connector_status status = connector_status_disconnected;
|
|
|
|
if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
|
|
return status;
|
|
|
|
intel_hdmi->has_hdmi_sink = false;
|
|
intel_hdmi->has_audio = false;
|
|
edid = drm_get_edid(connector,
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
intel_hdmi->ddc_bus));
|
|
|
|
if (edid) {
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
|
|
status = connector_status_connected;
|
|
if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
|
|
intel_hdmi->has_hdmi_sink =
|
|
drm_detect_hdmi_monitor(edid);
|
|
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
|
|
}
|
|
connector->display_info.raw_edid = NULL;
|
|
kfree(edid);
|
|
}
|
|
|
|
if (status == connector_status_connected) {
|
|
if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
|
|
intel_hdmi->has_audio =
|
|
(intel_hdmi->force_audio == HDMI_AUDIO_ON);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
static int intel_hdmi_get_modes(struct drm_connector *connector)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
|
|
/* We should parse the EDID data and find out if it's an HDMI sink so
|
|
* we can send audio to it.
|
|
*/
|
|
|
|
return intel_ddc_get_modes(connector,
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
intel_hdmi->ddc_bus));
|
|
}
|
|
|
|
static bool
|
|
intel_hdmi_detect_audio(struct drm_connector *connector)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
struct edid *edid;
|
|
bool has_audio = false;
|
|
|
|
edid = drm_get_edid(connector,
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
intel_hdmi->ddc_bus));
|
|
if (edid) {
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL)
|
|
has_audio = drm_detect_monitor_audio(edid);
|
|
|
|
connector->display_info.raw_edid = NULL;
|
|
kfree(edid);
|
|
}
|
|
|
|
return has_audio;
|
|
}
|
|
|
|
static int
|
|
intel_hdmi_set_property(struct drm_connector *connector,
|
|
struct drm_property *property,
|
|
uint64_t val)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
int ret;
|
|
|
|
ret = drm_connector_property_set_value(connector, property, val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (property == dev_priv->force_audio_property) {
|
|
enum hdmi_force_audio i = val;
|
|
bool has_audio;
|
|
|
|
if (i == intel_hdmi->force_audio)
|
|
return 0;
|
|
|
|
intel_hdmi->force_audio = i;
|
|
|
|
if (i == HDMI_AUDIO_AUTO)
|
|
has_audio = intel_hdmi_detect_audio(connector);
|
|
else
|
|
has_audio = (i == HDMI_AUDIO_ON);
|
|
|
|
if (i == HDMI_AUDIO_OFF_DVI)
|
|
intel_hdmi->has_hdmi_sink = 0;
|
|
|
|
intel_hdmi->has_audio = has_audio;
|
|
goto done;
|
|
}
|
|
|
|
if (property == dev_priv->broadcast_rgb_property) {
|
|
if (val == !!intel_hdmi->color_range)
|
|
return 0;
|
|
|
|
intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
|
|
goto done;
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
done:
|
|
if (intel_hdmi->base.base.crtc) {
|
|
struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
|
|
drm_crtc_helper_set_mode(crtc, &crtc->mode,
|
|
crtc->x, crtc->y,
|
|
crtc->fb);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intel_hdmi_destroy(struct drm_connector *connector)
|
|
{
|
|
drm_sysfs_connector_remove(connector);
|
|
drm_connector_cleanup(connector);
|
|
kfree(connector);
|
|
}
|
|
|
|
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
|
|
.dpms = intel_ddi_dpms,
|
|
.mode_fixup = intel_hdmi_mode_fixup,
|
|
.prepare = intel_encoder_prepare,
|
|
.mode_set = intel_ddi_mode_set,
|
|
.commit = intel_encoder_commit,
|
|
};
|
|
|
|
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
|
|
.dpms = intel_hdmi_dpms,
|
|
.mode_fixup = intel_hdmi_mode_fixup,
|
|
.prepare = intel_encoder_prepare,
|
|
.mode_set = intel_hdmi_mode_set,
|
|
.commit = intel_encoder_commit,
|
|
};
|
|
|
|
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
|
|
.dpms = drm_helper_connector_dpms,
|
|
.detect = intel_hdmi_detect,
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
.set_property = intel_hdmi_set_property,
|
|
.destroy = intel_hdmi_destroy,
|
|
};
|
|
|
|
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
|
|
.get_modes = intel_hdmi_get_modes,
|
|
.mode_valid = intel_hdmi_mode_valid,
|
|
.best_encoder = intel_best_encoder,
|
|
};
|
|
|
|
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
|
|
.destroy = intel_encoder_destroy,
|
|
};
|
|
|
|
static void
|
|
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
|
|
{
|
|
intel_attach_force_audio_property(connector);
|
|
intel_attach_broadcast_rgb_property(connector);
|
|
}
|
|
|
|
void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_connector *connector;
|
|
struct intel_encoder *intel_encoder;
|
|
struct intel_connector *intel_connector;
|
|
struct intel_hdmi *intel_hdmi;
|
|
|
|
intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
|
|
if (!intel_hdmi)
|
|
return;
|
|
|
|
intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
|
|
if (!intel_connector) {
|
|
kfree(intel_hdmi);
|
|
return;
|
|
}
|
|
|
|
intel_encoder = &intel_hdmi->base;
|
|
drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
|
|
DRM_MODE_ENCODER_TMDS);
|
|
|
|
connector = &intel_connector->base;
|
|
drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
|
|
DRM_MODE_CONNECTOR_HDMIA);
|
|
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_HDMI;
|
|
|
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
|
connector->interlace_allowed = 1;
|
|
connector->doublescan_allowed = 0;
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
|
|
|
/* Set up the DDC bus. */
|
|
if (sdvox_reg == SDVOB) {
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
|
|
dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
|
|
} else if (sdvox_reg == SDVOC) {
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
|
|
dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
|
|
} else if (sdvox_reg == HDMIB) {
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
|
|
dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
|
|
} else if (sdvox_reg == HDMIC) {
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
|
|
dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
|
|
} else if (sdvox_reg == HDMID) {
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
|
|
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
|
|
} else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
|
|
DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
|
|
intel_hdmi->ddi_port = PORT_B;
|
|
dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
|
|
} else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
|
|
DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
|
|
intel_hdmi->ddi_port = PORT_C;
|
|
dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
|
|
} else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
|
|
DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
|
|
intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
|
|
intel_hdmi->ddi_port = PORT_D;
|
|
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
|
|
} else {
|
|
/* If we got an unknown sdvox_reg, things are pretty much broken
|
|
* in a way that we should let the kernel know about it */
|
|
BUG();
|
|
}
|
|
|
|
intel_hdmi->sdvox_reg = sdvox_reg;
|
|
|
|
if (!HAS_PCH_SPLIT(dev)) {
|
|
intel_hdmi->write_infoframe = g4x_write_infoframe;
|
|
intel_hdmi->set_infoframes = g4x_set_infoframes;
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
|
intel_hdmi->write_infoframe = vlv_write_infoframe;
|
|
intel_hdmi->set_infoframes = vlv_set_infoframes;
|
|
} else if (IS_HASWELL(dev)) {
|
|
/* FIXME: Haswell has a new set of DIP frame registers, but we are
|
|
* just doing the minimal required for HDMI to work at this stage.
|
|
*/
|
|
intel_hdmi->write_infoframe = hsw_write_infoframe;
|
|
intel_hdmi->set_infoframes = hsw_set_infoframes;
|
|
} else if (HAS_PCH_IBX(dev)) {
|
|
intel_hdmi->write_infoframe = ibx_write_infoframe;
|
|
intel_hdmi->set_infoframes = ibx_set_infoframes;
|
|
} else {
|
|
intel_hdmi->write_infoframe = cpt_write_infoframe;
|
|
intel_hdmi->set_infoframes = cpt_set_infoframes;
|
|
}
|
|
|
|
if (IS_HASWELL(dev))
|
|
drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
|
|
else
|
|
drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
|
|
|
|
intel_hdmi_add_properties(intel_hdmi, connector);
|
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
|
|
* 0xd. Failure to do so will result in spurious interrupts being
|
|
* generated on the port when a cable is not attached.
|
|
*/
|
|
if (IS_G4X(dev) && !IS_GM45(dev)) {
|
|
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
|
|
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
|
|
}
|
|
}
|