Michael Tretter 9c789deea2 soc: xilinx: vcu: implement clock provider for output clocks ... The VCU System-Level Control uses an internal PLL to drive the core and MCU clock for the allegro encoder and decoder based on an external PL clock. In order be able to ensure that the clocks are enabled and to get their rate from other drivers, the module must implement a clock provider and register the clocks at the common clock framework. Other drivers are then able to access the clock via devicetree bindings. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-9-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2021-02-08 18:31:25 -08:00
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Kconfig	soc: xilinx: vcu: register PLL as fixed rate clock	2021-02-08 18:31:25 -08:00
Makefile	drivers: soc: xilinx: Add ZynqMP power domain driver	2019-02-12 13:38:16 +01:00
xlnx_vcu.c	soc: xilinx: vcu: implement clock provider for output clocks	2021-02-08 18:31:25 -08:00
zynqmp_pm_domains.c	firmware: xilinx: Remove eemi ops for set_requirement	2020-04-28 15:45:09 +02:00
zynqmp_power.c	soc: xilinx: Fix error code in zynqmp_pm_probe()	2020-06-18 10:07:17 +02:00