forked from Minki/linux
9bf49e36d7
Per PCIe r5.0, sec 9.3.7.11, VFs must not implement the PRI Capability. If the PF implements PRI, it is shared by the VFs. Since VFs don't have a PRI Capability, pci_enable_pri() always failed, which caused IOMMU setup to fail. Update the PRI interfaces so for VFs they reflect the state of the PF PRI. [bhelgaas: rebase without pri_cap caching, commit log] Suggested-by: Ashok Raj <ashok.raj@intel.com> Link: https://lore.kernel.org/r/b971e31f8695980da8e4a7f93e3b6a3edba3edaa.1567029860.git.sathyanarayanan.kuppuswamy@linux.intel.com Link: https://lore.kernel.org/r/20190905193146.90250-2-helgaas@kernel.org Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ashok Raj <ashok.raj@intel.com> Cc: Keith Busch <keith.busch@intel.com>
473 lines
10 KiB
C
473 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI Express I/O Virtualization (IOV) support
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* Address Translation Service 1.0
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* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
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* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
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*
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* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
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* Copyright (C) 2011 Advanced Micro Devices,
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*/
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#include <linux/export.h>
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#include <linux/pci-ats.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include "pci.h"
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void pci_ats_init(struct pci_dev *dev)
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{
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int pos;
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if (pci_ats_disabled())
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return;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
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if (!pos)
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return;
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dev->ats_cap = pos;
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}
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/**
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* pci_enable_ats - enable the ATS capability
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* @dev: the PCI device
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* @ps: the IOMMU page shift
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*
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* Returns 0 on success, or negative on failure.
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*/
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int pci_enable_ats(struct pci_dev *dev, int ps)
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{
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u16 ctrl;
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struct pci_dev *pdev;
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if (!dev->ats_cap)
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return -EINVAL;
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if (WARN_ON(dev->ats_enabled))
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return -EBUSY;
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if (ps < PCI_ATS_MIN_STU)
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return -EINVAL;
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/*
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* Note that enabling ATS on a VF fails unless it's already enabled
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* with the same STU on the PF.
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*/
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ctrl = PCI_ATS_CTRL_ENABLE;
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if (dev->is_virtfn) {
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pdev = pci_physfn(dev);
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if (pdev->ats_stu != ps)
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return -EINVAL;
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atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */
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} else {
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dev->ats_stu = ps;
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ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
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}
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pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
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dev->ats_enabled = 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_enable_ats);
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/**
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* pci_disable_ats - disable the ATS capability
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* @dev: the PCI device
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*/
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void pci_disable_ats(struct pci_dev *dev)
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{
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struct pci_dev *pdev;
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u16 ctrl;
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if (WARN_ON(!dev->ats_enabled))
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return;
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if (atomic_read(&dev->ats_ref_cnt))
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return; /* VFs still enabled */
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if (dev->is_virtfn) {
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pdev = pci_physfn(dev);
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atomic_dec(&pdev->ats_ref_cnt);
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}
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pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
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ctrl &= ~PCI_ATS_CTRL_ENABLE;
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pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
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dev->ats_enabled = 0;
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}
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EXPORT_SYMBOL_GPL(pci_disable_ats);
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void pci_restore_ats_state(struct pci_dev *dev)
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{
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u16 ctrl;
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if (!dev->ats_enabled)
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return;
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ctrl = PCI_ATS_CTRL_ENABLE;
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if (!dev->is_virtfn)
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ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
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pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
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}
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EXPORT_SYMBOL_GPL(pci_restore_ats_state);
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/**
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* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
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* @dev: the PCI device
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*
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* Returns the queue depth on success, or negative on failure.
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*
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* The ATS spec uses 0 in the Invalidate Queue Depth field to
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* indicate that the function can accept 32 Invalidate Request.
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* But here we use the `real' values (i.e. 1~32) for the Queue
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* Depth; and 0 indicates the function shares the Queue with
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* other functions (doesn't exclusively own a Queue).
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*/
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int pci_ats_queue_depth(struct pci_dev *dev)
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{
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u16 cap;
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if (!dev->ats_cap)
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return -EINVAL;
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if (dev->is_virtfn)
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return 0;
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pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
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return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
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}
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EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
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/**
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* pci_ats_page_aligned - Return Page Aligned Request bit status.
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* @pdev: the PCI device
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*
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* Returns 1, if the Untranslated Addresses generated by the device
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* are always aligned or 0 otherwise.
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*
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* Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
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* is set, it indicates the Untranslated Addresses generated by the
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* device are always aligned to a 4096 byte boundary.
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*/
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int pci_ats_page_aligned(struct pci_dev *pdev)
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{
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u16 cap;
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if (!pdev->ats_cap)
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return 0;
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pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
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if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
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return 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
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#ifdef CONFIG_PCI_PRI
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/**
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* pci_enable_pri - Enable PRI capability
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* @ pdev: PCI device structure
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*
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* Returns 0 on success, negative value on error
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*/
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int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
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{
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u16 control, status;
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u32 max_requests;
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int pos;
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/*
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* VFs must not implement the PRI Capability. If their PF
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* implements PRI, it is shared by the VFs, so if the PF PRI is
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* enabled, it is also enabled for the VF.
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*/
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if (pdev->is_virtfn) {
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if (pci_physfn(pdev)->pri_enabled)
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return 0;
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return -EINVAL;
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}
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if (WARN_ON(pdev->pri_enabled))
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return -EBUSY;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
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if (!(status & PCI_PRI_STATUS_STOPPED))
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return -EBUSY;
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pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
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reqs = min(max_requests, reqs);
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pdev->pri_reqs_alloc = reqs;
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pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
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control = PCI_PRI_CTRL_ENABLE;
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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pdev->pri_enabled = 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_enable_pri);
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/**
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* pci_disable_pri - Disable PRI capability
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* @pdev: PCI device structure
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*
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* Only clears the enabled-bit, regardless of its former value
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*/
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void pci_disable_pri(struct pci_dev *pdev)
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{
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u16 control;
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int pos;
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/* VFs share the PF PRI */
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if (pdev->is_virtfn)
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return;
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if (WARN_ON(!pdev->pri_enabled))
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return;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return;
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pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
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control &= ~PCI_PRI_CTRL_ENABLE;
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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pdev->pri_enabled = 0;
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}
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EXPORT_SYMBOL_GPL(pci_disable_pri);
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/**
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* pci_restore_pri_state - Restore PRI
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* @pdev: PCI device structure
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*/
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void pci_restore_pri_state(struct pci_dev *pdev)
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{
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u16 control = PCI_PRI_CTRL_ENABLE;
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u32 reqs = pdev->pri_reqs_alloc;
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int pos;
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if (pdev->is_virtfn)
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return;
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if (!pdev->pri_enabled)
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return;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return;
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pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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}
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EXPORT_SYMBOL_GPL(pci_restore_pri_state);
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/**
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* pci_reset_pri - Resets device's PRI state
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* @pdev: PCI device structure
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*
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* The PRI capability must be disabled before this function is called.
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* Returns 0 on success, negative value on error.
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*/
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int pci_reset_pri(struct pci_dev *pdev)
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{
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u16 control;
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int pos;
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if (pdev->is_virtfn)
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return 0;
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if (WARN_ON(pdev->pri_enabled))
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return -EBUSY;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return -EINVAL;
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control = PCI_PRI_CTRL_RESET;
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_reset_pri);
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/**
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* pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
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* status.
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* @pdev: PCI device structure
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*
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* Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
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*/
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int pci_prg_resp_pasid_required(struct pci_dev *pdev)
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{
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u16 status;
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int pos;
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if (pdev->is_virtfn)
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pdev = pci_physfn(pdev);
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return 0;
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pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
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if (status & PCI_PRI_STATUS_PASID)
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return 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_prg_resp_pasid_required);
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#endif /* CONFIG_PCI_PRI */
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#ifdef CONFIG_PCI_PASID
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/**
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* pci_enable_pasid - Enable the PASID capability
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* @pdev: PCI device structure
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* @features: Features to enable
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*
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* Returns 0 on success, negative value on error. This function checks
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* whether the features are actually supported by the device and returns
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* an error if not.
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*/
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int pci_enable_pasid(struct pci_dev *pdev, int features)
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{
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u16 control, supported;
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int pos;
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if (WARN_ON(pdev->pasid_enabled))
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return -EBUSY;
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if (!pdev->eetlp_prefix_path)
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return -EINVAL;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
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supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
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/* User wants to enable anything unsupported? */
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if ((supported & features) != features)
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return -EINVAL;
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control = PCI_PASID_CTRL_ENABLE | features;
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pdev->pasid_features = features;
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pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
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pdev->pasid_enabled = 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_enable_pasid);
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/**
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* pci_disable_pasid - Disable the PASID capability
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* @pdev: PCI device structure
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*/
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void pci_disable_pasid(struct pci_dev *pdev)
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{
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u16 control = 0;
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int pos;
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if (WARN_ON(!pdev->pasid_enabled))
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return;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return;
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pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
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pdev->pasid_enabled = 0;
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}
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EXPORT_SYMBOL_GPL(pci_disable_pasid);
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/**
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* pci_restore_pasid_state - Restore PASID capabilities
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* @pdev: PCI device structure
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*/
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void pci_restore_pasid_state(struct pci_dev *pdev)
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{
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u16 control;
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int pos;
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if (!pdev->pasid_enabled)
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return;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return;
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control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
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pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
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}
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EXPORT_SYMBOL_GPL(pci_restore_pasid_state);
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/**
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* pci_pasid_features - Check which PASID features are supported
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* @pdev: PCI device structure
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*
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* Returns a negative value when no PASI capability is present.
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* Otherwise is returns a bitmask with supported features. Current
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* features reported are:
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* PCI_PASID_CAP_EXEC - Execute permission supported
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* PCI_PASID_CAP_PRIV - Privileged mode supported
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*/
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int pci_pasid_features(struct pci_dev *pdev)
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{
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u16 supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
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supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
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return supported;
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}
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EXPORT_SYMBOL_GPL(pci_pasid_features);
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#define PASID_NUMBER_SHIFT 8
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#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
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/**
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* pci_max_pasid - Get maximum number of PASIDs supported by device
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* @pdev: PCI device structure
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*
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* Returns negative value when PASID capability is not present.
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* Otherwise it returns the number of supported PASIDs.
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*/
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int pci_max_pasids(struct pci_dev *pdev)
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{
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u16 supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
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supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
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return (1 << supported);
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}
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EXPORT_SYMBOL_GPL(pci_max_pasids);
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#endif /* CONFIG_PCI_PASID */
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